Publié il y a 8 jours
CAD Engineer (Conformal LEC)
@ Mirafra Technologies
Canada
En bref
Mirafra Technologies is hiring a full-time CAD Engineer for Logic Equivalence Checking (LEC) to build and support formal equivalence methodologies that verify functional correctness between RTL, synthesized netlists and physical designs in complex SoC development. The work covers owning LEC sign-off flows, enabling ECO flows, debugging non-equivalences, automating with scripts, and optimizing EDA verification tools. Schedule.
Responsabilités :
- Own and maintain end-to-end LEC sign-off methodologies
- Enable ECO flows for late-stage design changes
- Debug and resolve non-equivalences, aborts and mismatches
- Write and maintain automation scripts
- Optimize runtime and scalability of verification tools
Résumé des exigences :
- Bachelor's or Master's in Electrical Engineering, Computer Science or related field
- Dedicated hardware or EDA experience
- Proficiency in Cadence Conformal (LEC/ECO)
- Proficiency in Synopsys Formality
- Scripting in Tcl, Python, Perl or Shell
Outils et compétences
Source et dates
Type de source non vérifié · apify-linkedin
- Date publiée par l’employeur
- 2026-11-02
- Première détection par notre source
- 2026-11-10
- Mise à jour du dossier source
- 2026-11-10
Ces dates décrivent le dossier source, pas une vérification en direct du recrutement. Consultez l’offre originale.
Détails du poste
| Domaine | TI |
| Heures par semaine | 40 (estimé) |
| Milieu de travail | Bureau |
| Position | Surtout assis |
| Exigences physiques | physique faible · ordinateur élevé |
| Formation | Baccalauréat (exigé), Maîtrise (exigé) |
| Domaines d’études | Electrical Engineering, Computer Science |
Résumé et détails rédigés par l’IA à partir de l’offre; l’offre de l’employeur fait foi.
Mirafra Technologies
| Champ | Valeur |
|---|---|
| Offres sur Jobsy | 1 |
Job Description:
A LEC (Logic Equivalence Checking) CAD Engineer who will develop and support formal equivalence methodologies to ensure functional correctness between RTL, synthesized netlists, and physical designs in complex SoC (System on a Chip) development
Key Responsibilities
Flow Management: Own and maintain end-to-end LEC sign-off methodologies across RTL-to-GDS and gate-to-gate flows.
ECO Implementation: Enable Engineering Change Order (ECO) flows to ensure safe, correct late-stage design modifications.
Debugging & Root Cause: Analyze and resolve non-equivalences, aborts, and mismatches across design stages.
Automation: Write and maintain scripts and automation infrastructure using Tcl, Python, Perl, or Shell.
Tool Optimization: Optimize runtime, capacity, and scalability of verification tools while partnering with EDA vendors.
AI Enablement : Enable AI enabled tools and methodologies
Core Requirements
Tools Knowledge: Proficiency in industry-standard tools like Cadence Conformal (LEC/ECO) and Synopsys Formality.
Education: Bachelor's or Master’s degree in Electrical Engineering, Computer Science, or related fields with dedicated hardware/EDA experience
Journal
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