Publié il y a 2 mois
CPU Performance Modeling (Lead & ICs)
@ NUVACORE
Canada
En bref
NUVACORE is hiring a CPU Performance Modeling Lead, and senior individual contributors, to own its cycle-accurate CPU performance simulator and drive architectural decisions from pathfinding through tape-out and post-silicon correlation. The role covers microarchitectural exploration, model-to-RTL correlation, cross-team collaboration and mentoring. The posting requires an MS (PhD preferred) and 20+ years for Lead or 8+ years for ICs in CPU microarchitecture and performance engineering.
Responsabilités :
- Own cycle-accurate CPU performance simulator and roadmap
- Lead microarchitectural exploration across frontend, OOO and memory
- Drive model-to-RTL and post-silicon correlation
- Collaborate with design, verification and compiler teams
- Mentor performance engineers and provide technical leadership
Résumé des exigences :
- MS in computer architecture or related field (PhD preferred)
- 20+ years (Lead) or 8+ years (ICs) in CPU performance engineering
- Hands-on experience with cycle-accurate C++ simulators such as gem5
- Deep expertise in branch prediction, OOO, memory or prefetchers
- Strong C++, Python or Perl and assembly skills
- Track record from pathfinding through silicon
Outils et compétences
Source et dates
Site carrière / système de candidatures · lever
- Date publiée par l’employeur
- 2026-09-22
- Première détection par notre source
- 2026-10-08
- Mise à jour du dossier source
- 2026-10-26
Ces dates décrivent le dossier source, pas une vérification en direct du recrutement. Consultez l’offre originale.
Détails du poste
| Niveau | Chef d’équipe |
| Domaine | Génie |
| Expérience | 8 an(s) et plus |
| Gestion d’équipe | Oui |
| Heures par semaine | 40 (estimé) |
| Milieu de travail | Bureau |
| Position | Surtout assis |
| Exigences physiques | physique faible · ordinateur élevé |
| Langues | English |
| Formation | Maîtrise (exigé), Doctorat (préféré) |
| Domaines d’études | Computer Architecture, Computer Engineering |
Résumé et détails rédigés par l’IA à partir de l’offre; l’offre de l’employeur fait foi.
NUVACORE
Profil d’entreprise sauvegardé
Renseignements historiques provenant d’un profil The Jobs API sauvegardé (champs LinkedIn/Crunchbase). Ils ne sont pas vérifiés en temps réel; les chiffres peuvent avoir changé. Les valeurs manquantes restent inconnues.
NUVACORE is building a new class of CPU for the AI era, designed for maximum performance, efficiency, and scale.
Description complète de l’entreprise
Maximum performance. Absolute area efficiency. No compromise. A general-purpose CPU core designed to excel everywhere—from core infrastructure to advanced AI systems, including the continuous demands of agentic computing. This is not iteration, it is a complete rewrite of the rules of silicon.
- Abonnés LinkedIn
- 5 838
- Personnes associées sur LinkedIn
- 82
- Bureaux déclarés
- 5201 Great America Pkwy, Suite 215, San Jose, California 95054, US
- 5001 Plaza on the Lk, Suite 320, Austin, TX 78746, US
- 125 Commerce Valley Dr W, Suite 600, Markham, Ontario L3T 7W4, CA
- Autres noms enregistrés
- NUVACORE
- Le profil indique une agence de recrutement
- Non
Maximum performance. Absolute area efficiency. No compromise. A general-purpose CPU core designed to excel everywhere—from core infrastructure to advanced AI systems, including the continuous demands of agentic computing. This is not iteration, it is a complete rewrite of the rules of silicon.
| Champ | Valeur |
|---|---|
| Secteur | Technology, Information and Internet |
| Taille | 51-200 employees |
| Siège social | San Jose, California |
| Type d’organisation | Privately Held |
| Fondée en | 2026 |
| Offres sur Jobsy | 9 |
| Voir la page |
At NUVACORE we're designing a new general-purpose CPU core for the sustained, intensive demands of AI infrastructure and agentic computing, not the workloads of the past. As our CPU Performance Modeling Lead, you will own the performance modeling infrastructure and methodology that drives every architectural decision we make — from early pathfinding through tape-out and post-silicon correlation.
THE ROLE
Design, develop and own Nuvacore’s cycle-accurate CPU performance simulator — its architecture, fidelity, and long-term roadmap — as the authoritative reference model for the design team.
Lead microarchitectural exploration across all major CPU domains: frontend (fetch, decode, branch prediction), out-of-order engine (rename, dispatch, execution), and memory subsystem (caches, prefetchers, TLBs, coherence).
Drive model-to-RTL correlation through all execution phases; own debug and resolution of performance miscorrelation between the performance model, RTL simulation, and post-silicon results.
Collaborate closely with design, verification, compiler, and system software teams to align architecture decisions with implementation constraints and software stack realities.
Mentor engineers across the performance team; provide technical leadership on modeling methodology, simulation infrastructure, and analysis tooling.
Contribute to IP development through patents and, where applicable, external publication
REQUIREMENTS — MUST HAVE
MS in Computer Architecture, Computer Engineering, or related field (PhD preferred).
20+ years (Lead) or 8+ years (ICs) in CPU microarchitecture and/or performance engineering.
20+ years (Lead) or 8+ years (ICs) of hands-on experience with cycle-accurate C++ CPU performance simulators (e.g. gem5 or equivalent in-house tools).
Deep expertise in at least one of: branch prediction, fetch/decode, rename/dispatch, OOO execution, memory subsystem, or prefetchers.
Strong C++ and Python / Perl skills; ability to write and analyze assembly for microarchitectural test cases.
Proven track record driving performance from pathfinding through silicon (RTL correlation and/or post-Si debug).
Experience in RISC-V or ARM64 or x86 ISA.
Strong track record in identifying ideas to improve power/performance/area (PPA) of CPUs.
REQUIREMENTS — NICE TO HAVE
Experience with compiler optimizations and hardware/software co-design.
Published work or filed patents in CPU performance or microarchitecture.
Prior principal-level role at a CPU design organization.
The next great CPU won't build itself. We’re assembling a world-class team across every layer of CPU development, from architecture and design to verification, physical implementation, software, infrastructure, and product delivery. Every discipline matters, and every person has the opportunity to help shape the technology from the ground up.
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