Publié il y a 7 jours
Design Engineer
@ Dexian
Markham, Ontario
Responsabilités :
- Develop and implement power reduction strategies across SoC/IP design.
- Perform synthesis and static timing analysis (STA) to achieve PPA targets.
- Analyze and optimize dynamic and leakage power using industry-standard tools.
- Work closely with RTL designers, physical design, and verification teams to ensure timing and power requirements are met.
- Run low-power verification checks (UPF/CPF) and validate correct power intent implementation.
- Support sign-off activities for Lint , CDC , synthesis, timing, and power closure.
Résumé des exigences :
- You will use industry-standard EDA tools to optimize power, performance, and area (PPA), ensuring efficient, reliable silicon that meets product requirements.
- With strong analytical skills and a methodical approach, you are eager to learn, share knowledge, and contribute to building cutting-edge silicon.
- Work closely with RTL designers, physical design, and verification teams to ensure timing and power requirements are met.
- PREFERRED EXPERIENCE:
- Experience with power analysis and optimization techniques (clock gating, multi-Vt, power gating, multi-voltage design).
- Experience with advanced process nodes (e.g., 7nm, 5nm, 3nm) is a strong plus.
Source et dates
Type de source non vérifié · apify-linkedin
- Date publiée par l’employeur
- 2026-11-03
- Première détection par notre source
- 2026-11-10
- Mise à jour du dossier source
- 2026-11-10
Ces dates décrivent le dossier source, pas une vérification en direct du recrutement. Consultez l’offre originale.
Dexian
| Champ | Valeur |
|---|---|
| Offres sur Jobsy | 5 |
Job Title -ASIC/RTL Design Engineer 5#1023342
Duration: 12 Months
Location –Markham ON
THE ROLE:
In this role, you will be responsible for driving low-power design strategies, synthesis, and timing closure for complex SoC and IP designs. You will use industry-standard EDA tools to optimize power, performance, and area (PPA), ensuring efficient, reliable silicon that meets product requirements.
THE PERSON:
You are passionate about digital design, power optimization, and timing closure in advanced semiconductor technologies. You enjoy solving challenging problems, are detail-oriented, and thrive in a collaborative team environment and passionate to work with vibrant team located in different time zone . With strong analytical skills and a methodical approach, you are eager to learn, share knowledge, and contribute to building cutting-edge silicon.
KEY RESPONSIBILITIES:
- Develop and implement power reduction strategies across SoC/IP design.
- Perform synthesis and static timing analysis (STA) to achieve PPA targets.
- Analyze and optimize dynamic and leakage power using industry-standard tools.
- Work closely with RTL designers, physical design, and verification teams to ensure timing and power requirements are met.
- Run low-power verification checks (UPF/CPF) and validate correct power intent implementation.
- Support sign-off activities for Lint , CDC , synthesis, timing, and power closure.
- Automate and streamline power and timing workflows to improve efficiency.
- Build test plan documentation, accounting for interactions with other features, the hardware.
PREFERRED EXPERIENCE:
- Strong background in ASIC synthesis and static timing analysis (STA).
- Hands-on expertise with EDA tools such as Synopsys Design Compiler, PrimeTime, PrimePower, Power Artists , or equivalent.
- Experience with power analysis and optimization techniques (clock gating, multi-Vt, power gating, multi-voltage design).
- Familiarity with UPF/CPF power intent specification and verification.
- Solid understanding of digital design fundamentals, RTL coding (Verilog/SystemVerilog).
- Experience with advanced process nodes (e.g., 7nm, 5nm, 3nm) is a strong plus.
- Proficiency in scripting languages (TCL, Perl, Python, or Shell) for flow automation.
- Exposure to floorplanning, place-and-route, and ECO flows is desirable.
- Knowledge of low-power design methodologies and trade-offs.
- Prior leadership, mentorship, or cross-functional collaboration experience is an asset.
- Experienced with Verilog, System Verilog, C, and C++
- Graphics pipeline knowledge
- Automating workflows in a distributed compute environment.
About Dexian:Dexian stands at the forefront of Talent + Technology solutions with a presence spanning more than 70 locations worldwide and a team exceeding 10,000 professionals. As one of the largest technology and professional staffing companies and one of the largest minority-owned staffing companies in the United States, Dexian combines over 30 years of industry expertise with cutting-edge technologies to deliver comprehensive global services and support.
Dexian connects the right talent and the right technology with the right organizations to deliver trajectory-changing results that help everyone achieve their ambitions and goals.
To learn more, please visit https://dexian.com/.
Dexian is an Equal Opportunity Employer that recruits and hires qualified candidates without regard to race, religion, sex, sexual orientation, gender identity, age, national origin, ancestry, citizenship, disability, or veteran status.
Note: Dexian Canada will, on request, provide accommodations for disabilities to support
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