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Design Verification Engineer

@ LanceSoft, Inc.

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Markham, Ontario

Temps plein5+ ans d’expérience
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SIGNAUX

En bref

LanceSoft, Inc. is hiring a full-time Design Verification Engineer to verify complex ASICs and IP cores for a combined CPU/GPU development effort. The role requires at least 5 years of verification experience on large ASIC projects, strong C/C++ on Linux, and Verilog/SystemVerilog knowledge is preferred.

Responsabilités :

  • Verify functionality of complex ASIC and IP core blocks
  • Write and execute directed and constrained-random test plans
  • Document test plans and results
  • Adopt evolving industry verification methodologies
  • Work within existing verification infrastructure on active projects

Résumé des exigences :

  • 5+ years verification experience on large ASIC projects, or hardware-setting software experience
  • Strong C/C++ development on Linux
  • Debugging skills with Gdb and Valgrind
  • Knowledge of Perl and Makefiles
  • Experience with Verilog, SystemVerilog or SystemC preferred

Outils et compétences

GdbValgrindPerlMakefileVerilogSystemVerilogSystemC
Source et dates

Type de source non vérifié · apify-linkedin

Date publiée par l’employeur
Non fourni
Première détection par notre source
2026-11-15
Mise à jour du dossier source
2026-11-15

Ces dates décrivent le dossier source, pas une vérification en direct du recrutement. Consultez l’offre originale.

Détails du poste

NiveauSenior
DomaineGénie
Expérience5 an(s) et plus
Heures par semaine40 (estimé)
Milieu de travailBureau
PositionSurtout assis
Exigences physiquesphysique faible · ordinateur élevé
LanguesEnglish

Résumé et détails rédigés par l’IA à partir de l’offre; l’offre de l’employeur fait foi.

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LanceSoft, Inc.

Toutes ses offres
ChampValeur
Offres sur Jobsy17
Description

Participate in the functional verification of a block(s) of complex ASICs and/or IP cores for a combined CPU/GPU development effort. Be part of a team of design and verification engineers, working closely with other team members to understand and verify the functionality of a given design element within the context of the block, chip and overall system. Be responsible for carefully documenting and executing test plan(s) consisting of directed and constrained-random tests to be run during simulation. Be expected to adopt the evolving verification methodologies used in the industry to functionally verify increasingly more complex SoC designs within aggressive, market-driven schedules, and work within the existing verification infrastructure on currently active projects. Be familiar with hardware modeling and/or assertion-based verification methods.EXPERIENCE AND EDUCATION: Minimum 5 years of proven verification experience on large ASIC development projects or software/firmware experience in a hardware development setting;Strong background in C/C++ development in a Linux Environment;Strong debug skills and experience with debug tools such as Gdb, Valgrind;Proficient in Object Oriented programming, STL, computer architecture and data structures;Knowledge of Perl and Makefiles;Experience in Verilog/SystemVerilog/SystemC, preferred;Experience in C/Verilog environment using DPI/PLI, preferred;Strong analytical skills and attention to detail;Excellent written and communication skills.

EEO Employer

LanceSoft is a certified Minority Business Enterprise (MBE) and an equal opportunity employer. We prohibit discrimination and harassment of any kind based on race, color, sex, religion, sexual orientation, national origin, disability, genetic information, pregnancy, or any other protected characteristic as outlined by federal, state, or local laws.

This policy applies to all employment practices within our organization, including hiring, recruiting, promotion, termination, layoff, recall, leave of absence, compensation, benefits, training, and apprenticeship. LanceSoft makes hiring decisions based solely on qualifications, merit, and business needs at the time.

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