LEC (Logic Equivalence Checking) CAD Engineer

@ Mirafra Technologies

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Mirafra Technologies is hiring a LEC (Logic Equivalence Checking) CAD Engineer to develop and support formal equivalence methodologies that confirm functional correctness between RTL, synthesized netlists and physical designs in complex SoC development. The work covers owning LEC sign-off flows, enabling ECO flows, debugging non-equivalences, scripting automation and optimizing verification tools. The posting is a full-time role with no schedule, pay or work arrangement stated.

Responsabilités :

Own and maintain end-to-end LEC sign-off methodologies
Enable ECO flows for late-stage design modifications
Analyze and resolve non-equivalences and aborts
Write and maintain Tcl, Python, Perl or Shell automation
Optimize runtime and capacity of verification tools

Résumé des exigences :

Bachelor's or Master's in electrical engineering, computer science or related field
Dedicated hardware or EDA experience
Proficiency in Cadence Conformal (LEC/ECO)
Proficiency in Synopsys Formality

Outils et compétences

Cadence Conformal Synopsys Formality Tcl Python Perl Shell

Source et dates

Type de source non vérifié · apify-linkedin

Date publiée par l’employeur: 2026-10-15
Première détection par notre source: 2026-11-11
Mise à jour du dossier source: 2026-11-11

Ces dates décrivent le dossier source, pas une vérification en direct du recrutement. Consultez l’offre originale.

Détails du poste

Domaine	Génie
Heures par semaine	40 (estimé)
Milieu de travail	Bureau
Position	Surtout assis
Exigences physiques	physique faible · ordinateur élevé
Langues	English
Formation	Baccalauréat (exigé), Maîtrise (exigé)
Domaines d’études	Electrical Engineering, Computer Science

Résumé et détails rédigés par l’IA à partir de l’offre; l’offre de l’employeur fait foi.

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Mirafra Technologies

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Offres sur Jobsy	2

Description

A LEC (Logic Equivalence Checking) CAD Engineer who will develop and support formal equivalence methodologies to ensure functional correctness between RTL, synthesized netlists, and physical designs in complex SoC (System on a Chip) development

Key Responsibilities

Flow Management: Own and maintain end-to-end LEC sign-off methodologies across RTL-to-GDS and gate-to-gate flows.

ECO Implementation: Enable Engineering Change Order (ECO) flows to ensure safe, correct late-stage design modifications.

Debugging & Root Cause: Analyze and resolve non-equivalences, aborts, and mismatches across design stages.

Automation: Write and maintain scripts and automation infrastructure using Tcl, Python, Perl, or Shell.

Tool Optimization: Optimize runtime, capacity, and scalability of verification tools while partnering with EDA vendors.

AI Enablement : Enable AI enabled tools and methodologies

Core Requirements

Tools Knowledge: Proficiency in industry-standard tools like Cadence Conformal (LEC/ECO) and Synopsys Formality.

Education: Bachelor's or Master’s degree in Electrical Engineering, Computer Science, or related fields with dedicated hardware/EDA experience