Principal Analog Mixed Signal Designer - 19497

Date posted 11/04/2026

Category Engineering Hire Type Employee Job ID 19497 Base Salary Range $151200-$226800 Remote Eligible No Date Posted 11/04/2026

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years designing analog circuits that operate at the edge of what silicon can do, and you understand that a 224G SerDes is not just fast logic, it is a system of tradeoffs between power, jitter, linearity, and layout parasitics that all have to resolve correctly on the first pass. You know the difference between a PLL that locks in simulation and one that actually works across corners, temperature, and supply variation in a real package.

You think in both time and frequency domains without switching gears. When a layout comes back and the eye diagram collapses, you do not guess, you trace the signal path, check the return currents, and find the coupling that nobody else saw. You have debugged enough silicon to know that the gap between post-layout sim and bench measurement is where the real learning happens, and you treat that gap as data, not disappointment.

You are comfortable presenting a circuit architecture to a customer who will ask hard questions, and you can defend your choices without overselling. At Synopsys, you will work on SerDes IP that ships into products that matter, with a team that knows this space and expects you to push it forward.

What You'll Be Doing

• Define analog sub-block specifications for 224G and 448G PAM4 SerDes IP based on PCIe, Ethernet, and emerging industry standards
• Design and optimize circuit topologies for PLLs, CTLE and DFE equalizers, bang-bang and Mueller-Muller CDRs, and voltage or current-mode transmit drivers in advanced FinFET nodes
• Run transistor-level simulations in SPICE tools including corner sweeps, Monte Carlo analysis, and aging verification to ensure margin across all operating conditions
• Collaborate directly with layout engineers to control parasitics, manage signal routing, and maintain signal integrity in high-speed differential paths
• Present simulation results, design tradeoffs, and performance summaries to internal engineering teams and external customers during IP reviews
• Document circuit functionality, verification coverage, and integration test plans for handoff to digital and mixed-signal verification teams
• Perform hands-on lab characterization of SerDes silicon, analyze measurement data to isolate issues, determine root causes, and develop practical workarounds or design updates for the next revision

The Impact You Will Have

• Your circuit designs will directly determine the performance, power, and yield of SerDes IP used in data center, AI, and networking applications across the industry
• The specifications you define will shape how cross-functional teams build, verify, and integrate multi-gigabit interfaces into customer SoCs
• Your collaboration with layout will reduce parasitic-induced margin loss and enable first-pass silicon success on products with tight tapeout schedules
• The simulation rigor you bring will catch corner-case failures before they become silicon respins, saving months of schedule and significant engineering cost
• Your ability to debug silicon and translate bench results into actionable design changes will accelerate product maturity and customer adoption
• The documentation and test plans you create will enable verification and applications teams to confidently integrate and support your IP in production flows
• Your technical leadership will help set the direction for next-generation SerDes architectures as data rates continue to scale beyond 448G

What You'll Need

• PhD with 5+ years or Master's with 8+ years of hands-on analog IC design experience in Electrical Engineering, Computer Engineering, or a related field
• Deep transistor-level circuit design expertise with strong CMOS fundamentals and proven ability to design for performance, power, and area in advanced nodes
• Detailed design experience with at least two of the following SerDes sub-circuits: receive equalizers, samplers, voltage or current-mode drivers, serializers, deserializers, VCOs, phase mixers, DLLs, PLLs, bandgap references, ADCs, or DACs, and working familiarity with several others
• Proficiency with SPICE simulators and simulation methodologies including transient, AC, noise, and statistical analysis
• Experience with schematic entry, physical layout tools, and design verification flows used in custom analog IC development
• Knowledge of Verilog-A for analog behavioral modeling and simulation control or data capture is a plus
• Experience with scripting in TCL, Perl, Python, MATLAB, or C to automate simulation, analysis, or post-processing is desired

Who You Are

• You can walk into a layout review, spot a ground loop or a coupling path that will kill your phase noise by 10 dB, and explain exactly why it matters without sounding academic
• You do not treat Monte Carlo as a checkbox, you study the distributions, understand which parameters are driving yield loss, and know when to tighten a spec or change the topology
• You are comfortable sitting in a customer meeting where someone questions your jitter budget, and you can pull up the simulation, walk through the contributors, and defend your margin with data
• You treat documentation as part of the design, not an afterthought, because you know the next engineer who touches your block should not have to reverse-engineer your intent
• You have spent enough time in the lab to know that the first thing you check when the eye closes is not the circuit, it is the probe, the fixture, and the power supply sequencing
• You push back when a specification does not make sense or when a schedule assumes risk that has not been acknowledged, and you do it in a way that moves the conversation forward instead of shutting it down

The Team You'll Be Part Of

Your recruiter will share more about the team structure and mission during the interview process.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Synopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. Should you require an accommodation, please contact [email protected].