Publié il y a 6 jours
Senior RF engineer (Contract)
@ Per Vices Corporation
Toronto, Ontario
En bref
Per Vices Corporation is hiring a senior RF engineer on a 6-month contract, with an option to extend by 6 months. The work is designing and validating a wideband, high dynamic range RF transceiver front end and its clock distribution network, interfacing with an FPGA. The posting asks for deep high-frequency RF design experience and clear communication with the wider team.
Responsabilités :
- Design wideband, high dynamic range RF transceiver front end
- Design and validate clock distribution network using COTS components
- Interface RF front end with FPGA digital system
- Communicate design progress, challenges and updates to the broader team
Résumé des exigences :
- High-frequency (>20 GHz) RF front-end design experience
- Analog interface design for ADCs and DACs above 325 MSPS
- End-to-end RF board design and bring-up experience
- Working knowledge of C or C++
- Experience in at least three wideband RF or clock-distribution areas
Outils et compétences
Source et dates
Type de source non vérifié · apify-linkedin
- Date publiée par l’employeur
- 2026-11-04
- Première détection par notre source
- 2026-11-10
- Mise à jour du dossier source
- 2026-11-10
Ces dates décrivent le dossier source, pas une vérification en direct du recrutement. Consultez l’offre originale.
Détails du poste
| Niveau | Senior |
| Domaine | Génie |
| Milieu de travail | Laboratoire, Bureau |
| Position | Surtout assis |
| Exigences physiques | physique faible · ordinateur élevé |
Résumé et détails rédigés par l’IA à partir de l’offre; l’offre de l’employeur fait foi.
Per Vices Corporation
| Champ | Valeur |
|---|---|
| Offres sur Jobsy | 1 |
We are looking for an engineer to design, implement, and validate a flexible, wideband (greater than 6GHz), high dynamic range (more than 60dB) transceiver RF front end (amplifiers, attenuators, up/downconversion, ADC/DAC) and corresponding clock distribution network (using commercial off the shelf components) to interface with a digital system (FPGA), while effectively communicating the design, progress, challenges, and updates to a broader team.
Mandatory Skills
Experience in all of the following areas:
- High Frequency (>20GHz) RF front end design
- Experience designing analog interfaces to high speed ADCs and DACs (>325MSPS)
- End-to-end experience with design and manufacturing of RF boards (schematic capture, layout, initial bring up)
- Working knowledge of C or C++
Minimum Skills
Experience in at least three of the following areas:
- Transistor based LNA Design (<1.5dB)
- Wideband (DC-6GHz+) RF front end design
- Designing wideband matching networks (>2GHz BW)
- Designing wideband RF networks for RF/LO synthesizers (100MHz-6GHz+)
- Use of network analyzers to determine phase noise issues.
- Characterization and optimization of analog front end design
- Design of phase coherent clock distribution networks supporting >8 end devices
Optional Skills
The following skills are desired but not necessarily required for the position:
- Thermal management and passive cooling
- Familiarity with beam forming techniques
- Familiarity with phased arrays and their RF and analog implementation
- Knowledge of clock distribution and timing with JESD204 standard
- Experience designing low jitter (under 1 picosecond) clock distribution to digital and radio devices
- Experience designing low noise power systems (switching/linear regulators)
- Familiarity with antenna design and selection criteria for wideband or multiband applications
- Experience in development from design to manufacturing
- Experience with open source software
NOTE: This is a contractor position for 6 months with option for +6 month extension.
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