Publié il y a 18 mois
Senior Staff ASIC Design Egineer - AI/ML Hardware IP
@ Talentlab
Toronto, Ontario
En bref
Talentlab is hiring a Senior Staff ASIC Design Engineer for a global semiconductor leader to develop AI/ML hardware IP on-site in Canada. The role covers micro-architecture definition, RTL development, sub-IP integration across SoC designs, and cross-functional leadership of design and verification quality.
Responsabilités :
- Define and implement micro-architecture from AI/ML requirements
- Own RTL development in Verilog/SystemVerilog
- Integrate multiple sub-IP blocks into SoC systems
- Drive linting, CDC, synthesis and power intent flows
- Partner with verification teams on test plans and coverage
Résumé des exigences :
- 6+ years ASIC design, RTL and integration experience
- Advanced Verilog/SystemVerilog RTL skills
- Ownership of complex SoC blocks or subsystems
- Deep knowledge of simulation, CDC, formal and synthesis tools
- Bachelor's, Master's or PhD in electrical engineering or related field
- Legally authorized to work on-site in Canada
Outils et compétences
Source et dates
Type de source non vérifié · cats
- Date publiée par l’employeur
- 2025-06-02
- Première détection par notre source
- 2026-10-15
- Mise à jour du dossier source
- 2026-11-05
Ces dates décrivent le dossier source, pas une vérification en direct du recrutement. Consultez l’offre originale.
Détails du poste
| Niveau | Senior |
| Domaine | Génie |
| Expérience | 6 an(s) et plus |
| Milieu de travail | Bureau |
| Position | Surtout assis |
| Exigences physiques | physique faible · ordinateur élevé |
| Langues | English |
| Formation | Baccalauréat (exigé), Maîtrise (exigé), Doctorat (exigé) |
| Domaines d’études | Electrical Engineering |
Résumé et détails rédigés par l’IA à partir de l’offre; l’offre de l’employeur fait foi.
Talentlab
| Champ | Valeur |
|---|---|
| Offres sur Jobsy | 26 |
Position: Senior Staff ASIC Design Engineer – AI/ML Hardware IP
Location: On-site in Canada
We’re working with a global semiconductor leader to hire a Senior Staff ASIC Design Engineer focused on developing cutting-edge AI/ML hardware IP. This role is designed for a senior contributor who can lead architecture definition, RTL development, and integration across complex SoC designs. You'll work cross-functionally to optimize performance, area, power, and verification coverage in highly scalable AI/ML systems.
Key Responsibilities:
Define and implement micro-architecture based on high-level AI/ML design requirements.
Own RTL development (Verilog/SystemVerilog), optimizing for performance, area, and power.
Integrate multiple sub-IP blocks into cohesive larger systems.
Drive Linting, CDC, Synthesis, and Power Intent flow execution and analysis.
Partner closely with verification teams on test plans, debug, and functional coverage.
Develop SVA assertions to support formal and white-box verification strategies.
Influence and lead cross-functional execution, promoting best practices in design and integration.
Ideal Experience & Skills:
6+ years of ASIC design, RTL, and integration experience (or equivalent: Master’s + 5, PhD + 4).
Advanced RTL design skills, especially in Verilog/SystemVerilog.
Demonstrated ownership of complex SoC blocks or subsystems.
Strong background in:
Clock/reset architecture, FIFOs, memory control
Power-aware design and low-power optimization (UPF, CLP, PowerPro)
Bus protocols (AHB, AXI)
AI/ML-specific hardware acceleration blocks
Deep toolchain knowledge:
Simulation (VCS, Verdi, Questa, Xcelium)
CDC/lint/formal tools (Spyglass, 0-in, Formality)
Synthesis/timing (DCG/NXT, Primetime)
Scripting experience (Python, Perl, TCL, C) to support design automation.
Education & Work Authorization:
Bachelor’s, Master’s, or PhD in Electrical Engineering or related field.
Must be legally authorized to work on-site in Canada.
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