Staff Physical Design Engineer

Staff Physical Design Engineer

Our client is a leader in next-generation digital connectivity, enabling high-performance data communication across the most demanding industries—ranging from AI and the metaverse to data centers, 5G infrastructure, and autonomous vehicles. They deliver mission-critical IP through innovative engineering and a proven execution track record.

As a Staff Physical Design Engineer, you’ll take ownership of implementing, optimizing, and verifying complex digital designs at the physical level. You’ll work alongside front-end designers, DFT engineers, and verification teams to ensure the delivery of high-quality silicon. This role focuses on advanced-node physical implementation—floor planning, PnR, CTS, timing closure, and sign-off verification.

What You’ll Do

• Drive all stages of physical design including floor planning, placement, CTS, routing, and optimization for high-speed digital blocks.

• Own timing closure strategies, including skew balancing, delay optimization, and ECO implementation.

• Perform signal/power integrity analysis including IR drop and electromigration.

• Apply OPC litho shrink methodologies at advanced nodes such as TSMC N4P.

• Optimize designs for area and power using Multi-Vt, clock gating, and power-aware synthesis.

• Conduct physical verification (LVS, DRC, DFM) to meet foundry sign-off requirements.

• Collaborate across design, DFT, verification, and process teams to resolve implementation or manufacturability issues.

• Build and maintain automation scripts (TCL, Python, Perl) to streamline flows and improve efficiency.

What You’ll Need

• 5+ years of experience in physical design for digital ASICs.

• Hands-on experience with advanced nodes (TSMC N5/N4P/N3 or similar).

• Proficiency with industry-standard EDA tools: Synopsys ICC2, Cadence Innovus, Calibre, PrimeTime, RedHawk, etc.

• Deep understanding of PnR, CTS, STA, IR/EM analysis, and power optimization techniques.

• Experience with OPC shrink flows and advanced node methodologies.

• Familiarity with DFT techniques such as scan insertion, ATPG, or BIST is a plus.

• Experience with multi-patterning (LELE, SAQP) and full signoff verification (DRC, LVS, DFM, EM/IR, PEX).

• Strong scripting capabilities in TCL, Python, or Perl.

• Analytical mindset with a data-driven approach to debugging and problem-solving.

Preferred: Direct experience with FinFET technologies such as TSMC N5/N4/N4P/N3.

Please reach out to [email protected] with your resume if you're a fit for the position and interested in learning more.