System Level Test Engineer - 18758

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

We are seeking a System Level Test Engineerto own system-level silicon validation of DDR, LPDDR, and HBM memory interface IP in the lab. You bring up silicon, prove training, interoperability, and JEDEC timing across DRAM and HBM devices, and characterize margins at speed.

This is a hands-on technical role for someone who is equally comfortable with oscilloscope/VNA/BERT measurements, board-level design tradeoffs, and building automation to scale validation across PVT corners and product generations.

What You'll Be Doing

• Plan and execute system-level validation of DDR, LPDDR, and HBM IP on silicon, covering controller, PHY, and the attached memory device.
• Bring up new silicon and reference platforms: power, clocks, reset, training, link-up, and first read/write traffic for Protocol as the program requires.
• Characterize data eye, setup/hold, CA and DQ timing, voltage-frequency shmoo, and thermal corners. Call out what meets JEDEC or the IP spec, what is marginal, and what fails.
• Debug failures with oscilloscopes, logic or protocol analyzers, and on-chip status: training logs, error counters, and PHY or controller registers.
• Separate silicon, package, interposer or board, DRAM or HBM device, firmware, and test-setup causes.
• Automate Pipelines using Gitlab to speed up the Characterization and debug process.
• Write validation plans, test reports, and bug or errata entries that design and verification can reproduce. Track issues to closure across silicon spins.
• Support customer system debug when a DDR, LPDDR, or HBM failure maps back to IP behavior, and feed lab findings into the next IP drop and test content.
• Keep golden boards, HBM interposer or substrate setups, instrument configs, and known-good scripts in a state the rest of the lab can reuse.

The Impact You Will Have

• Your validation work directly determines whether Synopsys memory IP is ready to ship, affecting product timelines and customer confidence across the semiconductor industry
• The test automation you build scales across multiple IP products and releases, reducing validation cycle time and increasing coverage
• Your characterization reports become the technical foundation for customer engagements, sales collateral, and internal design reviews
• Debug rigor you bring to silicon issues prevents costly respins and field failures, protecting both schedule and reputation
• Test methodologies you develop and standardize become the playbook for future validation engineers joining the lab
• Customer issues you resolve keep high-stakes programs moving, often under tight timelines where your responsiveness is the difference between a delay and a win

• The data you collect and analyze feeds back into design improvements, tightening the loop between silicon and specification

What You'll Need

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field
• 3-5 years in silicon validation, applications, or system-level lab debug of memory interfaces.
• Hands-on silicon or board bring-up Experience
• Working knowledge of DRAM protocol and training: command/address, DQ/DQS or WDQS, ranks, bursts, refresh, and the usual training-fail signatures.
• Lab skill with a high-bandwidth oscilloscope, Power Analyzer, BERT, DMM etc.
• Scripting that drives the DUT and instruments. Python is preferred.
• Ability to read JEDEC timing tables, DRAM or HBM datasheets, board or substrate notes, and the IP programming guide, then turn them into a test.
• Debug write-ups that state the failing condition, the evidence, and whether the owner is design, verification, package, board, or the memory vendor.
• Signal-integrity basics on DQ, DQS, and CA: ISI, crosstalk, reflections, probe loading, and how layout or interposer routing works
• Interposer or CoWoS-style assembly constraints, lane repair, temperature gradient across the stack

Who You Are

• You can walk into a lab with a failing test case and walk out two hours later with a root cause and a plan, not just a theory
• You are comfortable presenting technical results to design teams, customers, and leadership, translating measurement data into clear conclusions without losing the nuance
• You manage multiple validation streams at once, keeping track of what is blocked, what is running, and what needs attention next without dropping threads
• You do not wait for perfect documentation or a fully defined test plan, you work with what you have, ask the right questions, and start collecting data

The Team You'll Be Part Of

You will join the growing Nepean lab team focused on validating Synopsys' memory interface IP portfolio. This is a hands-on lab environment where you will work closely with firmware and design groups to bring new IP from silicon bring-up through production release. The team operates at the intersection of design intent and real-world silicon behavior, and your work will directly inform product readiness and customer deployments.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.