Publié il y a 7 jours
Analog IC Layout Designer
@ Teledyne Digital Imaging, Inc.
Waterloo, Ontario
En bref
Teledyne Digital Imaging, Inc. is hiring an Analog IC Layout Designer, a full-time role creating transistor and block-level layouts for high-performance analog and mixed-signal ICs used in CMOS image sensors. The work covers floorplanning for matching, noise and reliability, running DRC and LVS signoff, and supporting tapeout alongside analog designers. The posting states a salary range of $93,700 to $124,900, with final pay based on location, experience and other factors.
Responsabilités :
- Create transistor- and block-level layouts for analog and mixed-signal circuits
- Optimize floorplans for matching, area, noise and reliability
- Run and resolve DRC, LVS, ERC and fill verification
- Support parasitic extraction, post-layout simulation and tapeout
- Collaborate with design, process and reliability teams
Résumé des exigences :
- 3+ years of analog/mixed-signal IC layout experience
- Bachelor's or Master's in EE, Computer Engineering, Physics or related field
- Proficiency with Cadence Virtuoso and Calibre, Assura or equivalent
- Experience with advanced CMOS technologies and signoff
- Advantage: ADC/DAC, PLL, CIS or low-noise sensor-interface experience
Outils et compétences
Source et dates
Site carrière / système de candidatures · workday
- Date publiée par l’employeur
- 2026-11-02
- Première détection par notre source
- 2026-10-30
- Mise à jour du dossier source
- 2026-11-03
Ces dates décrivent le dossier source, pas une vérification en direct du recrutement. Consultez l’offre originale.
Détails du poste
| Niveau | Intermédiaire |
| Domaine | Génie |
| Expérience | 3 an(s) et plus |
| Heures par semaine | 40 (estimé) |
| Milieu de travail | Bureau |
| Position | Surtout assis |
| Exigences physiques | physique faible · ordinateur élevé |
| Formation | Baccalauréat (exigé), Maîtrise (exigé) |
| Domaines d’études | Electrical Engineering, Computer Engineering, Physics |
Résumé et détails rédigés par l’IA à partir de l’offre; l’offre de l’employeur fait foi.
Teledyne Digital Imaging, Inc.
| Champ | Valeur |
|---|---|
| Offres sur Jobsy | 73 |
Be visionary
Teledyne Technologies Incorporated provides enabling technologies for industrial growth markets that require advanced technology and high reliability. These markets include aerospace and defense, factory automation, air and water quality environmental monitoring, electronics design and development, oceanographic research, deepwater oil and gas exploration and production, medical imaging and pharmaceutical research.
We are looking for individuals who thrive on making an impact and want the excitement of being on a team that wins.
Job Description
Join a team developing high-performance analog and mixed-signal ICs for CMOS image sensor applications. You’ll turn transistor-level designs into robust silicon layouts, balancing matching, noise, area, reliability, and manufacturability.
If you enjoy solving layout-dependent performance challenges and collaborating closely with analog designers from schematic through tapeout, this role offers meaningful technical depth within Teledyne Technologies.
What you’ll do
- Create transistor- and block-level layouts for Op-Amps, references, ADC/DACs, PLLs, sensor readout, and high-speed interfaces.
- Optimize floorplans for matching, area, noise isolation, power integrity, and EM reliability.
- Apply common-centroid, interdigitation, symmetry, shielding, guard-ring, and dummy-device techniques.
- Run and resolve DRC, LVS, ERC, density, and fill verification.
- Minimize parasitic coupling, process variation, and layout-dependent effects.
- Support parasitic extraction, post-layout simulation, and tapeout.
- Collaborate with design, process, reliability, verification, and CAD teams.
- Contribute to layout reviews and mentor junior engineers when appropriate.
What you need
- Required: Strong understanding of analog matching, parasitics, device physics, ESD, and reliability.
- Required: Ability to interpret transistor-level schematics and analog circuit behavior.
- Required: 3+ years of analog/mixed-signal IC layout experience.
- Required: Experience with advanced CMOS technologies and signoff.
- Required: Proficiency with Cadence Virtuoso and Calibre, Assura, or equivalent tools.
- Required: Bachelor’s or Master’s degree in EE, Computer Engineering, Physics, or related field.
- Advantage: CIS, ADC/DAC, PLL, high-voltage, or low-noise sensor-interface experience.
- Advantage: EM/IR, LDE, ESD/latch-up, advanced-node, and tapeout experience.
What we offer
- Technically challenging work on advanced sensor ICs.
- Collaboration across deep engineering disciplines.
- Opportunities to expand analog layout and silicon expertise.
- Exposure to designs from block level through integration and tapeout.
- The stability and engineering breadth of Teledyne Technologies.
What happens next
Applications are reviewed first, followed by a recruiter screen and technical/team interviews for selected candidates. Timelines vary by role and candidate availability.
Teledyne Technologies is an equal opportunity employer.
Salary Range:
$93,700.00-$124,900.000The anticipated salary range listed for this role is only an estimate. Actual compensation for successful candidates is carefully determined based on several factors including, but not limited to, location, local regulations (such as minimum wage), education/training, work experience, key skills, and type of position.
Teledyne and all of our employees are committed to conducting business with the highest ethical standards. We require all employees to comply with all applicable laws, regulations, rules and regulatory orders. Our reputation for honesty, integrity and high ethics is as important to us as our reputation for making innovative sensing solutions.
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