AI/ML Layout Engineering Intern (Winter 2027)
Ottawa, ONCiena Canada ULC
Candidates need to be enrolled in a Master's or PhD program in electrical, computer, or related engineering. They need a Python project they can explain, experience training a model with PyTorch, TensorFlow or scikit-learn, and coursework in algorithms and object-oriented programming.
Cadence Virtuoso, Git, Linux
Layout Design Co-op (Winter 2027)
Ottawa, ONCiena Canada ULC
Candidates need to be enrolled in an Electrical Engineering or related degree program, with experience in custom analog and mixed-signal layout. Knowledge of deep-submicron CMOS, layout matching and parasitics, and industry layout tools is also required.
Cadence Virtuoso, Siemens Calibre, SKILL
Mixed Signal Designer - coop
Ottawa, ONCiena Canada ULC
Ciena Canada ULC needs candidates actively enrolled in electrical or electronics engineering, with analog circuit theory, circuit simulation tool experience and lab equipment familiarity.
Spectre, Cadence Virtuoso, Xcelium, VCS, Questa, SystemVerilog
Lead Analog Layout Engineer
Ottawa, ONCiena Canada ULC
5+ ansCandidates need a Bachelor's degree or higher in Electrical Engineering or a related field and 5+ years of custom analog or mixed-signal IC layout experience, including completed tapeouts. Ciena requires hands-on skill with Cadence Virtuoso and Siemens Calibre, plus knowledge of matching, parasitics and deep-submicron CMOS.
Cadence Virtuoso, Siemens Calibre, Ansys Totem
Hardware Engineer - New Grad
Ottawa, ONCiena Canada ULC
Candidates need to be working toward a bachelor's, master's or PhD in electrical engineering or a related science, with prior internship, co-op or project experience. Strong analog design skills in BiCMOS or CMOS, proficiency with Cadence, Mentor and Synopsys tools, and good English communication are required.
Cadence Virtuoso, Calibre, STAR-RC, MMSIM, Synopsys, Mentor
Analog and Mixed-Signal Modelling Architect (Masters or PhD New Grad)
Ottawa, ONCiena Canada ULC
Candidates need a post-graduate degree in Physics or Engineering focused on ASIC hardware, communication or control systems, plus an internship, co-op or applied project. They need C++ or SystemC modelling experience and knowledge of analog impairments such as noise, jitter and phase noise.
C++, SystemC-AMS, Python, MATLAB, Simulink, Cadence Virtuoso
Senior Analog Layout Engineer
Ottawa, ONCiena Canada ULC
Ciena Canada ULC needs a candidate with a bachelor's degree in engineering or science and industrial experience in high-speed analog layout in advanced BiCMOS or CMOS. Candidates must work well alone and in teams, use Cadence, Mentor, and Synopsys tools, and communicate clearly in English.
Cadence Virtuoso, Calibre PERC, Calibre PEX, Synopsys tools