Publié il y a 2 mois
CPU Verification Engineer
@ NUVACORE
Markham, Ontario
En bref
NUVACORE is hiring CPU Verification Engineers at Senior and Principal levels to prove the correctness of its new high-performance, low-power CPU. The role builds test plans, environments and checkers that find pipeline bugs before silicon, working with architecture and RTL design. Full-time.
Responsabilités :
- Drive verification scope, strategy and test plans for the CPU
- Build and scale verification environments, checkers and coverage
- Generate and debug directed and random tests, including assembly and RIS
- Correlate RTL against performance models
- Define coverage space and analyze closure metrics
Résumé des exigences :
- Degree in electrical/computer engineering or computer science, or equivalent experience
- 4+ years (Senior) or 15+ years (Principal) of design verification
- Strong CPU microarchitecture and digital logic knowledge
- Proficiency in C/C++ or SystemVerilog plus Python
- Experience writing and debugging assembly tests
Outils et compétences
Source et dates
Site carrière / système de candidatures · lever
- Date publiée par l’employeur
- 2026-09-18
- Première détection par notre source
- 2026-10-08
- Mise à jour du dossier source
- 2026-10-09
Ces dates décrivent le dossier source, pas une vérification en direct du recrutement. Consultez l’offre originale.
Détails du poste
| Niveau | Senior |
| Domaine | Génie |
| Expérience | 4 an(s) et plus |
| Heures par semaine | 40 (estimé) |
| Milieu de travail | Bureau, Laboratoire |
| Position | Surtout assis |
| Exigences physiques | physique faible · ordinateur élevé |
| Langues | English |
| Formation | Baccalauréat (exigé) |
| Domaines d’études | Electrical Engineering, Computer Engineering, Computer Science |
Résumé et détails rédigés par l’IA à partir de l’offre; l’offre de l’employeur fait foi.
NUVACORE
Profil d’entreprise sauvegardé
Renseignements historiques provenant d’un profil The Jobs API sauvegardé (champs LinkedIn/Crunchbase). Ils ne sont pas vérifiés en temps réel; les chiffres peuvent avoir changé. Les valeurs manquantes restent inconnues.
NUVACORE is building a new class of CPU for the AI era, designed for maximum performance, efficiency, and scale.
Description complète de l’entreprise
Maximum performance. Absolute area efficiency. No compromise. A general-purpose CPU core designed to excel everywhere—from core infrastructure to advanced AI systems, including the continuous demands of agentic computing. This is not iteration, it is a complete rewrite of the rules of silicon.
- Abonnés LinkedIn
- 5 838
- Personnes associées sur LinkedIn
- 82
- Bureaux déclarés
- 5201 Great America Pkwy, Suite 215, San Jose, California 95054, US
- 5001 Plaza on the Lk, Suite 320, Austin, TX 78746, US
- 125 Commerce Valley Dr W, Suite 600, Markham, Ontario L3T 7W4, CA
- Autres noms enregistrés
- NUVACORE
- Le profil indique une agence de recrutement
- Non
Maximum performance. Absolute area efficiency. No compromise. A general-purpose CPU core designed to excel everywhere—from core infrastructure to advanced AI systems, including the continuous demands of agentic computing. This is not iteration, it is a complete rewrite of the rules of silicon.
| Champ | Valeur |
|---|---|
| Secteur | Technology, Information and Internet |
| Taille | 51-200 employees |
| Siège social | San Jose, California |
| Type d’organisation | Privately Held |
| Fondée en | 2026 |
| Offres sur Jobsy | 9 |
| Voir la page |
Nuvacore is building a ground-up high performance, low-power CPU for next-generation compute workloads. We are seeking Verification Engineers at multiple levels — from Senior Engineer to Principal level — to help prove the correctness of the Nuvacore CPU. As part of the design verification (DV) team, you will help verify by building the test plans, environments, and checkers that find deep bugs in the pipeline long before silicon, working shoulder-to-shoulder with architecture and RTL design.
THE ROLE
Plan & Strategy: Drive the verification scope, strategy, and test plans for the CPU at unit and/or top level of the CPU design.
Environment Setup: Build, maintain, and scale robust verification environments — stimulus generators, checkers, transactors, and coverage — that exercise the pipeline end to end.
Test & Debug: Generate complex directed and random tests in assembly, C, or random instruction sequences (RIS) to expose corner cases such as speculation, hazards, flushes, and retirement ordering.
Performance Verification: Partner with architects to correlate RTL against performance models, hunting throughput, stall, and branch-prediction-accuracy issues.
Coverage Closure: Define the coverage space, write functional coverage monitors, and analyze metrics to prove the test plan is complete.
Cross-functional Collaboration: Partner with architecture and RTL teams to root-cause failures, drive design fixes, and support emulation, FPGA, and silicon bring-up.
REQUIREMENTS — MUST HAVE
Degree in Electrical/Computer Engineering, Computer Science, or equivalent practical experience.
15+ years (Principal) or 4+ years (Senior Engineer) of design-verification experience, ideally on a CPU or complex digital design.
Strong knowledge of CPU micro-architecture and digital logic — pipelines, out-of-order execution, and branch prediction.
Hands-on functional verification: test plans, testbenches, checkers, transactors, and coverage.
Proficiency in C/C++ and/or SystemVerilog, plus a scripting language (Python; Perl a plus).
Experience writing and debugging tests in assembly for CPU verification.
REQUIREMENTS — NICE TO HAVE
Experience on one or more of Front-end / execution-unit verification, load/store cache verification, SoC/System verification, Debug/Power mgmt verification.
Random instruction sequence (RIS) stimulus generation.
Constrained-random verification and coverage-driven closure.
Assertions and formal verification.
Emulation/FPGA and silicon bring-up and debug (waveforms, trace).
Driving a verification problem end-to-end to sign-off.
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