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Publié il y a 8 jours

Design Verification Engineer (PCIe)

@ HCLTech

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Canada

Temps plein
Postuler
SIGNAUX

En bref

HCLTech is hiring a full-time Design Verification Engineer for PCIe in Canada. The role builds SystemVerilog and UVM verification environments to verify PCIe Gen3/Gen4/Gen5 protocols and debug design issues to closure. The posting asks for strong SystemVerilog/UVM experience and PCIe protocol knowledge.

Responsabilités :

  • Build SystemVerilog and UVM verification environments
  • Verify PCIe Gen3/Gen4/Gen5 protocol compliance
  • Create assertions, coverage models and constrained-random tests
  • Debug design and protocol issues to closure
  • Collaborate with design and architecture teams

Résumé des exigences :

  • Strong SystemVerilog and UVM design verification experience
  • Hands-on PCIe Gen3/Gen4/Gen5 verification
  • Knowledge of PCIe architecture, LTSSM and protocol layers
  • Exposure to AXI, APB and AHB
  • Experience with VCS, Xcelium or Questa
  • Excellent debugging and problem-solving skills

Outils et compétences

SystemVerilogUVMVCSXceliumQuesta
Source et dates

Type de source non vérifié · apify-linkedin

Date publiée par l’employeur
2026-11-02
Première détection par notre source
2026-11-10
Mise à jour du dossier source
2026-11-10

Ces dates décrivent le dossier source, pas une vérification en direct du recrutement. Consultez l’offre originale.

Détails du poste

DomaineGénie
Heures par semaine40 (estimé)
Déplacementsavion : aucun · route : aucun
Milieu de travailBureau
PositionSurtout assis
Exigences physiquesphysique faible · ordinateur élevé
LanguesEnglish

Résumé et détails rédigés par l’IA à partir de l’offre; l’offre de l’employeur fait foi.

Postuler
ChampValeur
Offres sur Jobsy14
Description

🚀 Hiring: Design Verification Engineer (PCIe) | Canada

Are you passionate about cutting-edge semiconductor and high-speed interface technologies? We are looking for a Design Verification (DV) Engineer with strong expertise in SystemVerilog (SV), UVM, and PCIe verification to join a dynamic engineering team.

Key Responsibilities:

✅ Design and develop robust verification environments using SystemVerilog and UVM

✅ Verify PCIe Gen3/Gen4/Gen5 protocols and ensure compliance with specifications

✅ Develop reusable verification components, testbenches, and methodologies

✅ Create and maintain assertions (SVA), coverage models, and constrained-random test scenarios

✅ Debug complex design and protocol issues and drive them to closure

✅ Collaborate closely with design and architecture teams

Required Skills:

  • Strong experience in Design Verification using SystemVerilog (SV) and UVM
  • Hands-on experience in PCIe Gen3/Gen4/Gen5 protocol verification
  • Strong understanding of:
  • PCIe Architecture
  • LTSSM
  • Transaction Layer
  • Data Link Layer
  • Physical Layer
  • Exposure to AXI, APB, and AHB protocols
  • Experience developing reusable verification environments and VIPs
  • Knowledge of SVA, coverage-driven verification, and constrained-random methodologies
  • Experience with simulators such as VCS, Xcelium, or Questa
  • Excellent debugging, analytical, and problem-solving skills

📩 Interested candidates can apply directly or send their updated resume. Connect with me to learn more!

#Hiring #DesignVerification #DVEngineer #SystemVerilog #UVM #PCIe #PCIeGen5 #Semiconductor #ASIC #SoC #VerificationEngineer #RTLVerification #HardwareEngineering #TechJobs #CanadaJobs #HCLTech

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