Connexion Inscription gratuite
Postuler

Publié hier

Physical Design Engineer

@ Mirafra Technologies

Toutes ses offres

Canada

Temps plein
Postuler
SIGNAUX

En bref

Mirafra Technologies is hiring a full-time Physical Design Engineer focused on static timing analysis, timing closure on sub-nanometer nodes, and automating physical design flows in Tcl and Python with AI-assisted coding tools. The role requires a degree in electrical, computer or microelectronics engineering and strong STA and scripting skills.

Responsabilités :

  • Execute static timing analysis and timing signoff across implementation phases
  • Write and maintain Tcl and Python scripts for EDA tool flows
  • Analyze setup, hold, crosstalk, IR drop and clock path issues
  • Collaborate with RTL and synthesis teams on PPA optimization
  • Build regression tests and document automated methodologies

Résumé des exigences :

  • Bachelor's or Master's in electrical, computer or microelectronics engineering
  • In-depth STA knowledge with SDC and signoff tools
  • Strong Tcl and Python coding skills
  • Experience with Copilot or LLM-driven coding tools
  • Sound knowledge of digital CMOS and PnR flows

Outils et compétences

PrimeTimeTempusICC2Fusion CompilerInnovusGitHub CopilotGit
Source et dates

Type de source non vérifié · apify-linkedin

Date publiée par l’employeur
2026-11-12
Première détection par notre source
2026-11-14
Mise à jour du dossier source
2026-11-14

Ces dates décrivent le dossier source, pas une vérification en direct du recrutement. Consultez l’offre originale.

Détails du poste

DomaineGénie
Heures par semaine40 (estimé)
Milieu de travailBureau
PositionSurtout assis
Exigences physiquesphysique faible · ordinateur élevé
FormationBaccalauréat (exigé), Maîtrise (exigé)
Domaines d’étudesElectrical Engineering, Computer Engineering, Microelectronics

Résumé et détails rédigés par l’IA à partir de l’offre; l’offre de l’employeur fait foi.

Postuler

Mirafra Technologies

Toutes ses offres
ChampValeur
Offres sur Jobsy4
Description

Role Overview

We are seeking a Physical Design Engineer with a strong foundation in Static Timing Analysis (STA) and a focus on design flow automation. In this role, you will be responsible for driving timing closure across complex, sub-nanometer process nodes while leveraging next-generation development tools. You will play a key role in developing, optimizing, and automating physical design workflows using Tcl and Python, incorporating AI-assisted development tools like GitHub Copilot to accelerate script delivery and engineering efficiency.

Key Responsibilities

  • Static Timing Analysis (STA): Execute timing signoff, constraint validation, multi-corner multi-mode (MCMM) analysis, and timing closure across all phases of physical implementation.
  • Flow Automation & Scripting: Write, maintain, and enhance robust automated scripts using Tcl and Python to streamline EDA tool flows (place & route, synthesis, signoff).
  • AI-Assisted Development: Utilize Copilot-assisted development tools to rapidly build, refactor, and test flow automation scripts, optimizing operational productivity.
  • Timing & Power Optimization: Analyze setup/hold violations, crosstalk, IR drop, and clock path issues, collaborating closely with RTL and synthesis teams to achieve optimal PPA (Power, Performance, Area).
  • Process Improvement: Standardize scripting frameworks, build continuous regression tests for physical design tools, and document automated methodologies for the broader team.

Qualifications

Required Skills & Experience:

  • Education: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Microelectronics, or a related field.
  • Core STA Expertise: In-depth understanding of Static Timing Analysis principles, timing constraints (SDC), clock jitter, skew, cross-talk noise, and signoff methodologies using industry tools (e.g., Synopsys PrimeTime or Cadence Tempus).
  • Scripting Proficiency: Strong hands-on coding ability in Tcl (for EDA tool integration) and Python (for data processing and workflow automation).
  • Modern Development Tooling: Direct experience or strong familiarity with Copilot-assisted coding/script development tools (or LLM-driven coding tools) to write, debug, and optimize scripts efficiently.
  • VLSI Fundamentals: Sound understanding of digital CMOS logic, place and route (PnR) flow fundamentals, and physical verification concepts.

Preferred Qualifications:

  • Experience with automated tool API integrations (e.g., Synopsys ICC2/Fusion Compiler, Cadence Innovus APIs).
  • Experience implementing CI/CD pipelines or automated regression frameworks for hardware design flows.
  • Background in Git or modern version control systems for managing Tcl/Python script repositories.

Emplois semblables

  • Physical Design Engineer

    Vancouver, BC
    Contrat

    Chiparama

    5+ ansCandidates need 5+ years of hands-on ASIC physical design experience, a BS or MS in electrical engineering, computer engineering or computer science, and experience with industry EDA tools. Scripting in Tcl, Python or Perl and eligibility to work in Canada are also required.

    Synopsys, Cadence, Calibre, ICV

  • Physical Design Engineer, Staff

    Toronto, ON
    Sur place

    Qualcomm Canada ULC

    7+ ansCandidates need 7+ years of physical design experience and a Bachelor's in Electrical or Computer Engineering or equivalent. Low-power, SoC and advanced technology node experience are desired, along with strong analytical, scripting and collaboration skills.

    EDA tools

  • Physical Design Engineer

    Vancouver, BC
    Temps plein

    AMD, Inc.

    Candidates need hands-on ASIC physical design experience from RTL to GDSII, strong Verilog and timing analysis skills, and tape-out experience on advanced nodes such as 3nm, 5nm, 7nm or 16nm. A bachelor's or master's degree in computer or electrical engineering is required.

    Synopsys, Cadence, Mentor Graphics, Verilog

    Physical Design Engineer

    Markham, ON
    Temps plein

    AMD, Inc.

    8+ ansCandidates need a degree in electrical, electronics or computer engineering, with 8 or more years of physical design experience (or 4 with a master's, or 2 with a PhD). They must have hands-on expertise in place and route, timing closure, physical verification and debugging CAD flows with industry tools such as Synopsys, Cadence and Mentor Graphics.

    Synopsys ICC2, Innovus, PrimeTime, Spyglass, RedHawk, VSI

    Physical Design Engineer

    Markham, ON
    Temps plein

    AMD, Inc.

    Candidates need hands-on ASIC physical design experience from RTL to GDSII, strong Verilog and timing analysis skills, and tape-out experience on advanced nodes such as 3nm, 5nm, 7nm or 16nm. A bachelor's or master's degree in computer or electrical engineering is required.

    Synopsys, Cadence, Mentor Graphics, Verilog

  • Physical Design Engineer - Synth, Senior

    Télétravail au Canada
    TélétravailTemps plein

    Positron AI

    8+ ansCandidates need 8+ years of ASIC implementation experience, including at least two tapeouts, and strong synthesis and timing-closure experience on large designs. Expertise with Genus or Design Compiler, SDC constraints, Tcl and Python scripting, and advanced process nodes (7nm and below preferred) is required.

    Cadence Genus, Synopsys Design Compiler, Tcl, Python

  • Physical Design Engineer

    Vancouver, BC
    Temps plein

    Advanced Micro Devices, Inc

    Candidates need a bachelor's or master's degree in computer or electrical engineering and hands-on ASIC physical design experience from RTL to GDSII. Strong Verilog, timing analysis, low-voltage design and advanced-node tape-out experience (3nm to 16nm) are preferred.

    Synopsys tools, Cadence tools, Mentor Graphics tools, Verilog

    Physical Design Engineer

    Markham, ON
    Temps plein

    Advanced Micro Devices, Inc

    8+ ansCandidates need a bachelor's, master's or PhD in electrical, electronics or computer engineering, with 8, 4 or 2 years of physical design experience respectively. They need expertise in block-level place and route, timing closure, physical verification and power, performance and area optimization, plus hands-on debugging of EDA tools from Synopsys, Cadence and Siemens.

    Synopsys ICC2, Cadence Innovus, Synopsys PrimeTime, Spyglass, RedHawk, Calibre

Lieux et modes de travail

Lieux

Tout le CanadaTélétravail · Hybride · Sur place · Sur le terrain

Astuce : ajoutez le télétravail pour élargir la recherche.

Exclure des lieux

Mode de travail

Offres de cette entreprise dans les résultats

Voici les offres de cette entreprise chargées dans votre recherche. Elle peut avoir d’autres postes ouverts.