Connexion Inscription gratuite
Postuler

Publié hier

Physical Design Engineer

@ Chiparama

Toutes ses offres

Vancouver, Colombie-Britannique

Contrat5+ ans d’expérience
Postuler
SIGNAUX

En bref

Chiparama is hiring a Physical Design Engineer (ASIC) on a 12 to 18 month contract in Vancouver, BC, working onsite with an ASIC Physical Design team. The role owns full-chip physical implementation from RTL to GDSII on advanced technology nodes, including timing signoff, IR/EM analysis and physical verification. The posting requires 5+ years of hands-on ASIC physical design experience and eligibility to work in Canada.

Responsabilités :

  • Own full-chip physical design from RTL to GDSII
  • Drive static timing analysis and timing signoff
  • Perform IR drop, EM and physical verification
  • Optimize designs for power, performance and area
  • Build and improve physical design automation flows

Résumé des exigences :

  • 5+ years of ASIC physical design experience
  • BS or MS in EE, CE or CS
  • Hands-on experience with Synopsys and Cadence EDA tools
  • Scripting in Tcl, Python or Perl
  • Eligible to work in Canada

Outils et compétences

SynopsysCadenceCalibreICV
Source et dates

Type de source non vérifié · apify-linkedin

Date publiée par l’employeur
2026-11-12
Première détection par notre source
2026-11-14
Mise à jour du dossier source
2026-11-14

Ces dates décrivent le dossier source, pas une vérification en direct du recrutement. Consultez l’offre originale.

Détails du poste

NiveauSenior
DomaineGénie
Expérience5 an(s) et plus
Déplacementsavion : aucun · route : aucun
Milieu de travailBureau
PositionSurtout assis
Exigences physiquesphysique faible · ordinateur élevé
LanguesEnglish
FormationBaccalauréat (exigé), Maîtrise (exigé)
Domaines d’étudesElectrical Engineering, Computer Engineering, Computer Science

Résumé et détails rédigés par l’IA à partir de l’offre; l’offre de l’employeur fait foi.

Postuler
ChampValeur
Offres sur Jobsy1
Description

🚀 We’re Hiring: Physical Design Engineer (ASIC)

📍 Vancouver, BC, Canada (Onsite)

📄 Contract: 12–18 months

We’re hiring a Physical Design Engineer for a leading global networking and semiconductor company. You’ll join an ASIC Physical Design team and own full-chip physical implementation from RTL to GDSII on advanced technology nodes.

What you’ll do

🔹 Own physical design implementation of multi-hierarchy designs: physical-aware synthesis, DFT, floorplanning, placement, CTS and routing

🔹 Drive Static Timing Analysis (STA) and timing signoff closure

🔹 Perform IR Drop/EM analysis and physical verification (DRC/LVS) through signoff

🔹 Optimize designs for Power, Performance and Area (PPA)

🔹 Work with Front-End/RTL teams to understand the design architecture and resolve implementation issues

🔹 Build and improve automation scripts and physical design flows

What we’re looking for

✅ BS/MS in Electrical Engineering, Computer Engineering or Computer Science

✅ 5+ years of hands-on ASIC physical design and implementation experience

✅ Strong skills in floorplanning, PnR, CTS, timing closure and hierarchical design

✅ Hands-on experience with industry-standard EDA tools (Synopsys, Cadence; Calibre/ICV for PV)

✅ Experience with EM/IR and physical verification signoff

✅ Scripting in Tcl, Python or Perl

✅ Eligible to work in Canada

Nice to have

➕ Formal verification (LEC) experience

➕ Experience with advanced nodes (5nm/3nm) and complex SoC integration

📩 Interested? DM me or comment “Interested” and I’ll reach out. Referrals are welcome!

Equal Employment Opportunity: We are an equal opportunity employer. All qualified applicants will be considered for employment without regard to race, colour, religion, sex, sexual orientation, gender identity or expression, national origin, age, disability, Indigenous status, veteran status, or any other characteristic protected by applicable law. We are committed to an inclusive and accessible hiring process. Accommodations are available on request at any stage.

#Hiring #PhysicalDesign #ASIC #VLSI #Semiconductor #RTLtoGDSII #STA #VancouverJobs #CanadaJobs #ContractJobs #HardwareEngineering

Emplois semblables

  • Physical Design Engineer

    Canada
    Temps plein

    Mirafra Technologies

    Candidates need a bachelor's or master's degree in electrical, computer or microelectronics engineering. They need deep static timing analysis knowledge, strong Tcl and Python coding skills, and familiarity with AI coding assistants.

    PrimeTime, Tempus, ICC2, Fusion Compiler, Innovus, GitHub Copilot

  • Physical Design Engineer, Staff

    Toronto, ON
    Sur place

    Qualcomm Canada ULC

    7+ ansCandidates need 7+ years of physical design experience and a Bachelor's in Electrical or Computer Engineering or equivalent. Low-power, SoC and advanced technology node experience are desired, along with strong analytical, scripting and collaboration skills.

    EDA tools

  • Physical Design Engineer

    Vancouver, BC
    Temps plein

    AMD, Inc.

    Candidates need hands-on ASIC physical design experience from RTL to GDSII, strong Verilog and timing analysis skills, and tape-out experience on advanced nodes such as 3nm, 5nm, 7nm or 16nm. A bachelor's or master's degree in computer or electrical engineering is required.

    Synopsys, Cadence, Mentor Graphics, Verilog

    Physical Design Engineer

    Markham, ON
    Temps plein

    AMD, Inc.

    8+ ansCandidates need a degree in electrical, electronics or computer engineering, with 8 or more years of physical design experience (or 4 with a master's, or 2 with a PhD). They must have hands-on expertise in place and route, timing closure, physical verification and debugging CAD flows with industry tools such as Synopsys, Cadence and Mentor Graphics.

    Synopsys ICC2, Innovus, PrimeTime, Spyglass, RedHawk, VSI

    Physical Design Engineer

    Markham, ON
    Temps plein

    AMD, Inc.

    Candidates need hands-on ASIC physical design experience from RTL to GDSII, strong Verilog and timing analysis skills, and tape-out experience on advanced nodes such as 3nm, 5nm, 7nm or 16nm. A bachelor's or master's degree in computer or electrical engineering is required.

    Synopsys, Cadence, Mentor Graphics, Verilog

  • Physical Design Engineer - Synth, Senior

    Télétravail au Canada
    TélétravailTemps plein

    Positron AI

    8+ ansCandidates need 8+ years of ASIC implementation experience, including at least two tapeouts, and strong synthesis and timing-closure experience on large designs. Expertise with Genus or Design Compiler, SDC constraints, Tcl and Python scripting, and advanced process nodes (7nm and below preferred) is required.

    Cadence Genus, Synopsys Design Compiler, Tcl, Python

  • Physical Design Engineer

    Vancouver, BC
    Temps plein

    Advanced Micro Devices, Inc

    Candidates need a bachelor's or master's degree in computer or electrical engineering and hands-on ASIC physical design experience from RTL to GDSII. Strong Verilog, timing analysis, low-voltage design and advanced-node tape-out experience (3nm to 16nm) are preferred.

    Synopsys tools, Cadence tools, Mentor Graphics tools, Verilog

    Physical Design Engineer

    Markham, ON
    Temps plein

    Advanced Micro Devices, Inc

    8+ ansCandidates need a bachelor's, master's or PhD in electrical, electronics or computer engineering, with 8, 4 or 2 years of physical design experience respectively. They need expertise in block-level place and route, timing closure, physical verification and power, performance and area optimization, plus hands-on debugging of EDA tools from Synopsys, Cadence and Siemens.

    Synopsys ICC2, Cadence Innovus, Synopsys PrimeTime, Spyglass, RedHawk, Calibre

Lieux et modes de travail

Lieux

Tout le CanadaTélétravail · Hybride · Sur place · Sur le terrain

Astuce : ajoutez le télétravail pour élargir la recherche.

Exclure des lieux

Mode de travail

Offres de cette entreprise dans les résultats

Voici les offres de cette entreprise chargées dans votre recherche. Elle peut avoir d’autres postes ouverts.