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Publié il y a 8 jours

RTL Design Engineer

@ HCLTech

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Canada

Temps plein
Postuler
SIGNAUX

En bref

HCLTech is hiring an RTL Design Engineer in Canada to develop Verilog/SystemVerilog RTL and PCIe Gen3/Gen4/Gen5 designs. The role covers micro-architecture definition, RTL implementation, debugging and performance optimization, working with cross-functional teams across the design lifecycle. Full-time; location is Canada.

Responsabilités :

  • Develop and implement RTL designs in Verilog/SystemVerilog
  • Work on PCIe Gen3/Gen4/Gen5 design and verification
  • Contribute to micro-architecture definition and RTL implementation
  • Perform debugging, validation and performance optimization
  • Collaborate with cross-functional teams

Résumé des exigences :

  • Hands-on RTL design in Verilog/SystemVerilog
  • Hands-on PCIe protocol experience (Gen3/Gen4/Gen5 preferred)
  • Understanding of FSM, pipelining, CDC, reset architecture, synchronizers, low-power design
  • Micro-architecture and RTL implementation experience
  • Knowledge of synthesis constraints and timing
  • Familiarity with Lint, CDC, STA and low-power verification

Outils et compétences

VerilogSystemVerilog
Source et dates

Type de source non vérifié · apify-linkedin

Date publiée par l’employeur
2026-11-02
Première détection par notre source
2026-11-11
Mise à jour du dossier source
2026-11-11

Ces dates décrivent le dossier source, pas une vérification en direct du recrutement. Consultez l’offre originale.

Détails du poste

Heures par semaine40 (estimé)
Milieu de travailBureau
PositionSurtout assis
Exigences physiquesphysique faible · ordinateur élevé

Résumé et détails rédigés par l’IA à partir de l’offre; l’offre de l’employeur fait foi.

Postuler
ChampValeur
Offres sur Jobsy20
Description

We're looking for a talented RTL Design Engineer with strong expertise in Verilog/SystemVerilog and PCIe protocol design/verification to join our growing team.

If you have a passion for digital design, micro-architecture development, and solving complex hardware challenges, we'd love to connect with you!

🔹 Key Responsibilities:

  • Develop and implement RTL designs using Verilog/SystemVerilog.
  • Work on PCIe (Gen3/Gen4/Gen5) design and verification activities.
  • Contribute to micro-architecture definition and RTL implementation.
  • Perform debugging, validation, and performance optimization.
  • Collaborate with cross-functional teams throughout the design lifecycle.

🔹 Required Skills:

✅ Strong hands-on experience in RTL Design using Verilog/SystemVerilog

✅ Hands-on experience with PCIe protocols (Gen3/Gen4/Gen5 preferred)

✅ Solid understanding of digital design fundamentals:

  • FSM Design
  • Pipelining
  • Clock Domain Crossing (CDC)
  • Reset Architecture
  • Synchronizers
  • Low-Power Design Concepts

✅ Experience in micro-architecture development and RTL implementation

✅ Knowledge of synthesis constraints and timing concepts

✅ Familiarity with Lint, CDC, STA, and low-power verification methodologies

✅ Strong debugging and problem-solving skills

📍 Location: Canada

If you're interested or know someone who would be a great fit, please reach out directly or send your updated resume.

#RTLDesign #Verilog #SystemVerilog #PCIe #Semiconductor #VLSI #ASICDesign #HardwareEngineering #DigitalDesign #Hiring #CanadaJobs #HCLTech #TechCareers

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