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Première détection par notre source: il y a 22 jours

RTL Design Engineer - AI Tools

@ Mercor

Toutes ses offres Site Web

Toronto, Ontario

100–175 $/h3+ ans d’expérience
Postuler
SIGNAUX

En bref

Mercor is hiring an RTL Design Engineer on a remote, 40-hour-per-week contract of 3 or more months at $100 to $175 per hour. The role evaluates digital chip design workflows to improve AI model training, designs and verifies RTL components in Verilog and SystemVerilog, and uses LLM-based tools to speed up design and verification.

Salaire :

100 $–175 $ de l’heure

Responsabilités :

  • Evaluate digital chip design workflows for AI model training
  • Design and verify RTL components in Verilog and SystemVerilog
  • Develop reusable verification components and testbench infrastructure
  • Collaborate with architecture and verification teams
  • Use LLM-based tools to accelerate design and verification

Résumé des exigences :

  • 3 to 10 years of digital RTL design or design verification
  • Strong Verilog, SystemVerilog and UVM proficiency
  • Understanding of FSMs, datapaths, pipelines and bus protocols
  • Experience with ASIC design flows and EDA tools
  • Clear design documentation and communication skills

Outils et compétences

VerilogSystemVerilogUVMEDA tools
Source et dates

Type de source non vérifié · manatal

Date publiée par l’employeur
Non fourni
Première détection par notre source
2026-10-18
Mise à jour du dossier source
2026-10-18

Ces dates décrivent le dossier source, pas une vérification en direct du recrutement. Consultez l’offre originale.

Détails du poste

NiveauIntermédiaire
DomaineGénie
Expérience3 an(s) et plus
Heures par semaine40
Déplacementsavion : aucun · route : aucun
Milieu de travailDomicile
PositionSurtout assis
Exigences physiquesphysique faible · ordinateur élevé
LanguesEnglish

Résumé et détails rédigés par l’IA à partir de l’offre; l’offre de l’employeur fait foi.

Postuler

Mercor

Profil d’entreprise sauvegardé

Renseignements historiques provenant d’un profil The Jobs API sauvegardé (champs LinkedIn/Crunchbase). Ils ne sont pas vérifiés en temps réel; les chiffres peuvent avoir changé. Les valeurs manquantes restent inconnues.

We connect human expertise with leading AI labs and enterprises to train frontier models.

Description complète de l’entreprise

Mercor is defining the future of work. We connect human expertise with leading AI labs and enterprises to train frontier models.

Abonnés LinkedIn
654 507
Personnes associées sur LinkedIn
5 250
Bureaux déclarés
  • San Francisco, California 94105, US
Catégories d’activité
  • Employment
  • Software
  • Recruiting
  • Data Collection and Labeling
  • Artificial Intelligence (AI)
  • Machine Learning
Autres noms enregistrés
  • Mercor
Le profil indique une agence de recrutement
Oui
Investissement total déclaré
483 600 000

La devise et la date d’observation ne sont pas fournies; ce n’est ni une valorisation actuelle ni une ronde de financement.

Toutes ses offres Site Web

Mercor is defining the future of work. We connect human expertise with leading AI labs and enterprises to train frontier models.

ChampValeur
SecteurSoftware Development
Taille51-200 employees
Siège socialSan Francisco, California
Type d’organisationPrivately Held
Fondée en2023
Offres sur Jobsy1 626
LinkedInVoir la page
Description

About the job

Mercor connects elite creative and technical talent with leading AI research labs. Headquartered in San Francisco, our investors include Benchmark, General Catalyst, Peter Thiel, Adam D'Angelo, Larry Summers, and Jack Dorsey.

Position: RTL Design Engineers
Type: Contract
Compensation: $100–$175/hour
Location: Remote
Duration: 3+ months
Commitment: 40 hours/week

Role Responsibilities

  • Evaluate digital chip design workflows to enhance AI model training and evaluation.
  • Design and verify RTL components using Verilog/SystemVerilog.
  • Collaborate with architecture, verification, and implementation teams to improve model outputs.
  • Develop reusable verification components and testbench infrastructure.
  • Leverage LLM-based tools to accelerate chip design and verification processes.
  • Work independently and asynchronously to meet project deadlines.

Qualifications

Must-Have

  • 3–10 years of experience in digital RTL design or design verification.
  • Strong proficiency in Verilog/SystemVerilog and UVM.
  • Solid understanding of digital design fundamentals: FSMs, datapaths, pipelines, FIFOs, arbiters, clock/reset domains, bus protocols.
  • Experience with ASIC design flows and common EDA tools.
  • Ability to write clear design documentation and communicate technical tradeoffs.

Preferred

  • Knowledge of AMBA protocols (AXI, AHB, APB).
  • Background in CPU, GPU/ML accelerator, networking, memory subsystem, PCIe/high-speed IO, SoC interconnect, low-power design.
  • Exposure to formal verification or SV/UVM-based design verification.

Start Date

  • Week of 04/23; applications reviewed on a rolling basis.

Compensation & Legal

  • Hourly contractor, Paid weekly.

Application Process (Takes 20–30 mins to complete)

  • Upload resume
  • AI interview based on your resume
  • Submit form

Resources & Support

  • For details about the interview process and platform information, please check: https://talent.docs.mercor.com/welcome
  • For any help or support, reach out to: [email protected]

PS: Our team reviews applications daily. Please complete your AI interview and application steps to be considered for this opportunity.

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