Standard Cell Design Enablement Lead

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At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.

Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career.

THE ROLE:

This role is part of a team that is responsible for developing Standard Cell Libraries, supporting 3^RD party Standard Cell Libraries for all AMD products, and in-house Process Characterization structures. These IPs must meet AMD’s performance, power, area, and cost requirements in state-of-the-art CMOS technologies. We are exposed to bleeding-edge technologies that few other companies will ever hear of. We play a major role in shaping AMD’s roadmap and future products.

This team is essential to the success of AMD as a growing company. It is a very exciting environment, and you will be working with the very best in our technology. You will be working on some of the most exciting projects the industry has to offer.

THE PERSON:

In-depth knowledge of semiconductor device physics and fabrication processes, strong analytical and problem-solving skills related to semiconductor device performance, ability to collaborate effectively with design, layout, and verification teams, exceptional written and oral communication skills in English.

RESPONSIBILITIES:

• Communication with external standard cell library vendor regarding schedules, requirements, SOW (statement of work)
• Driving communication with our external standard cell library vendors and internal customers related to library release schedules and contents, questions and issues.
• Oversight of download, build, release, QA of libraries.
• Coordinate the effort to download, build, release and QA vendor standard cell libraries, as well as driving discussion for internally developed cells from our customers.
• Addressing requests and issues for standard cells.

PREFERRED EXPERIENCE:

• Standard cell design and layout analysis.
• Proficiency in industry-standard EDA (SNPS/CDNS/Siemens) tools for PDK (product development kit), DRC (design rule check) , LVS (layout vs schematic), Virtuoso, PEX, capacitance modeling, and EMIR and reliability analysis.
• Experience with IR Drop analysis techniques and tools.
• Schematic and layout entry, physical and logical verification, extraction, timing characterization using industry standard EDA tools in advanced semiconductor processes, coupled with the ability to leverage Unix shell environments and scripting languages such as Perl and Python.
• Experience with SPICE simulation and familiarity with industry-standard modeling techniques.
• Proficiency in Unix shell environments, Perl, and Python scripting.

ACADEMIC CREDENTIALS:

• MSEE/MSCS in related field

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Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.