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ASIC Verification Engineer

@ Nokia

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Ottawa, Ontario

HybrideTemps plein8+ ans d’expérience
Postuler
SIGNAUX

En bref

Nokia is hiring an ASIC Verification Engineer for its Optical Networks division to verify complex SoCs, ASICs and FPGAs. The role involves building SystemVerilog/UVM test environments, writing test plans, and supporting hardware and software bring-up and debug. It requires a Bachelor's in CS or EE and at least 8 years of ASIC verification experience.

Responsabilités :

  • Define, develop and execute self-checking tests for complex digital ASICs
  • Build SystemVerilog/UVM protocol and traffic generators and checkers
  • Write test plans from functional and standards requirements
  • Support HW/SW bring-up and debug with system and supplier teams

Résumé des exigences :

  • Bachelor's degree in CS or EE required, Master's desired
  • 8+ years of ASIC verification experience
  • Intimate knowledge of UVM methodology
  • Fluent in SystemVerilog and Python

Outils et compétences

UVMPythoncode coverage toolsformal verification tools

Avantages mentionnés

Soins de la vue
Source et dates

Site carrière / système de candidatures · oraclecloud

Date publiée par l’employeur
2026-10-02
Première détection par notre source
2026-10-08
Mise à jour du dossier source
2026-10-09

Ces dates décrivent le dossier source, pas une vérification en direct du recrutement. Consultez l’offre originale.

Détails du poste

NiveauSenior
DomaineGénie
Expérience8 an(s) et plus
Heures par semaine40 (estimé)
Milieu de travailBureau
PositionSurtout assis
Exigences physiquesphysique faible · ordinateur élevé
LanguesEnglish
FormationBaccalauréat (exigé), Maîtrise (préféré)
Domaines d’étudesComputer Science, Electrical Engineering

Résumé et détails rédigés par l’IA à partir de l’offre; l’offre de l’employeur fait foi.

Postuler
ChampValeur
Offres sur Jobsy75
Description

We are seeking an ASIC Verification Engineer with a solid ASIC/FPGA verification test strategy & development and debugging skills."The Network Infrastructure group is at the heart of a revolution to connectivity, pushing the boundaries to deliver more and faster network capacity to people worldwide through our ambition, innovation, and technical expertise​. Join Optical Networks division, where innovation meets scale in the AI-driven data center era. With the recent acquisition of Infinera, we’ve united two industry leaders to create an optical networking powerhouse—combining cutting-edge technology with proven leadership to redefine the future of connectivity.

  • Working as independent contributor in development and verification of the world leading SoCs based on latest technology ASICs and FPGAs

  • Working on System Verilog/UVM-based protocol/traffic generators/checkers

  • Working on test plan based on functional requirements as well as applicable standards requirements

  • Working with experts of different areas to ensure the most competitive solutions

  • Cooperating with system engineers, HW/SW development, suppliers and other relevant functions to solve technical issues

  • Supporting HW/SW bring-up and debug

  • Work as an independent contributor or lead a team to deliver defined tasks.
  • Masters degree desired, Bachelor's degree in CS/EE is required.
  • Minimum 8+ years of relevant experience in the ASIC verification field.
  • Should have worked on developing/implementing test plans at the block or sub-chip levels for complex ASICs.
  • Fluent in System Verilog and scripting languages such as Python.
  • Must have intimate knowledge of UVM methodology.
  • Knowledgeable about assertions and functional coverage Experience with code coverage and formal verification tools; familiarity with evolving verification methodologies.
  • Strong problem solving skills.
  • Very good communication skills and ability and desire to work in a geographically diverse team environment.
  • Will be responsible for the definition, development, and execution of self-checking tests for complex digital ASICs.
  • Knowledge of DSP and/or FEC will be desirable.

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