Design Verification Engineer

Emplois semblables

• 1j

  Design Verification Engineer (PCIe)

  Canada

  Temps plein

  H

  HCLTech

  Candidates need hands-on SystemVerilog and UVM design verification experience and PCIe Gen3/Gen4/Gen5 protocol verification skills, with knowledge of PCIe architecture, LTSSM and the transaction, data link and physical layers. Strong debugging and analytical skills are also required.

  SystemVerilog, UVM, VCS, Xcelium, Questa

• 25j

  Design Verification Engineer - Fully Remote | Upto $175/hr

  Toronto, ON

  100–175 $/h

  

  Mercor

  3+ ansCandidates need 3 to 10 years of digital RTL design or design verification experience, strong Verilog/SystemVerilog and UVM skills, and solid knowledge of digital design fundamentals. They also need ASIC design flow experience and the ability to write clear design documentation.

  Verilog, SystemVerilog, UVM, EDA tools

• 28j

  Senior Design Verification Engineer

  Toronto, ON

  T

  Talentlab

  3+ ansTalentlab needs candidates with 3 to 8 years of design verification experience and strong SystemVerilog and UVM skills. Experience with SerDes, DSP or mixed-signal designs is needed, and Ethernet and PCIe knowledge is a strong plus.

  SystemVerilog, UVM, Python, Perl, C/C++, GNU Make

• 28j

  Design Verification Engineer

  Markham, ON

  Temps plein

  AI

  AMD, Inc.

  AMD asks for advanced ASIC functional verification experience and hands-on work on multiple projects or tapeouts. Candidates need Verilog, SystemVerilog, UVM, scripting skills, and a Bachelor's or Master's in Computer or Electrical Engineering.

  Verilog, UVM, Makefiles, Perl, Python, Ruby

• 1 mois

  Design Verification Engineer, Annapurna Labs

  Toronto, ON

  Temps plein

  AD

  Amazon Development Centre Canada ULC

  4+ ansCandidates need a bachelor's degree in electrical engineering or a related field and at least 4 years of design verification experience using constrained-random simulation such as UVM. Strong debugging skills across IP, SoC and full-system levels are required.

  UVM, Python, Perl, C++

  1 mois

  Design Verification Engineer - technical lead, Annapurna Labs

  Toronto, ON

  Temps plein

  AD

  Amazon Development Centre Canada ULC

  8+ ansCandidates need a bachelor's degree in electrical engineering or a related field and 8+ years of constrained-random verification experience (such as UVM), including testbench development. Experience across IP, SoC and full-system verification, plus formal, emulation or scripting skills, is highly desired.

  UVM, formal verification tools, emulation platforms, Python, Perl

• 1 mois

  Design Verification Engineer

  Markham, ON

  Temps plein

  AM

  Advanced Micro Devices, Inc

  Candidates need hands-on hardware verification experience across multiple projects or tapeouts, with SystemVerilog, UVM, Verilog and scripting skills. A Bachelor's or Master's in Computer or Electrical Engineering is expected.

  UVM, Verilog, Makefiles, Perl, Python, Ruby

• 1 mois

  Design Verification Engineer — Memory Subsystem (Vancouver)

  Vancouver, BC

  Sur place

  

  Qualcomm Canada ULC

  3+ ansCandidates need a bachelor's or master's degree in an engineering or computer science field and 3 to 10 years of chip or subsystem verification experience. Hands-on skill with Verilog, SystemVerilog, UVM and assertions is required, and knowledge of memory standards such as DDR, LPDDR and HBM is preferred.

  Verilog, SystemVerilog, UVM, SystemVerilog Assertions, waveform viewers