Publié il y a 7 mois
DV - Staff Verification Engineer - Serdes
@ Eliyan
Canada
En bref
Eliyan is hiring a Staff Design Engineer to lead verification of SerDes and other PHYs for chiplet-based systems. The role covers verification planning, UVM/SystemVerilog testbenches and technical mentoring of junior engineers. The posting requires onsite work Monday to Friday and a security clearance (DV).
Responsabilités :
- Develop and execute verification plans for SerDes, PHYs and DSP blocks
- Create and maintain SystemVerilog/UVM verification environments
- Write and debug UVM test cases for block and chip level
- Lead verification of TX/RX equalization and CDR
- Mentor junior verification engineers
Résumé des exigences :
- BS plus 7 years of verification experience
- 4+ years in PHY or high-speed interfaces
- Deep SerDes/PCIe PHY verification expertise
- Strong UVM/SystemVerilog and assertion coding skills
- Experience verifying mixed-signal IPs and integrating VIPs
Outils et compétences
Source et dates
Site carrière / système de candidatures · lever
- Date publiée par l’employeur
- 2026-04-07
- Première détection par notre source
- 2026-10-08
- Mise à jour du dossier source
- 2026-10-15
Ces dates décrivent le dossier source, pas une vérification en direct du recrutement. Consultez l’offre originale.
Détails du poste
| Niveau | Senior |
| Domaine | Génie |
| Expérience | 7 an(s) et plus |
| Heures par semaine | 40 (estimé) |
| Horaire | jour |
| Milieu de travail | Bureau |
| Position | Surtout assis |
| Exigences physiques | physique faible · ordinateur élevé |
| Langues | English |
| Formation | Baccalauréat (exigé) |
| Cote de sécurité | Autre cote |
Résumé et détails rédigés par l’IA à partir de l’offre; l’offre de l’employeur fait foi.
Eliyan
Profil d’entreprise sauvegardé
Renseignements historiques provenant d’un profil The Jobs API sauvegardé (champs LinkedIn/Crunchbase). Ils ne sont pas vérifiés en temps réel; les chiffres peuvent avoir changé. Les valeurs manquantes restent inconnues.
Accelerating a Smarter Future by Revolutionizing Chiplet-based Systems
Description complète de l’entreprise
Eliyan's mission is to revolutionize chiplet connectivity technologies by challenging the status quo to unleash the ultimate performance of smart systems of the future.
- Abonnés LinkedIn
- 5 761
- Personnes associées sur LinkedIn
- 82
- Bureaux déclarés
- Santa Clara, US
- Catégories d’activité
- Electronics
- Semiconductor
- Manufacturing
- Autres noms enregistrés
- Eliyan
- Eliyan Corporation
- Le profil indique une agence de recrutement
- Non
- Investissement total déclaré
- 150 000 000
La devise et la date d’observation ne sont pas fournies; ce n’est ni une valorisation actuelle ni une ronde de financement.
Eliyan's mission is to revolutionize chiplet connectivity technologies by challenging the status quo to unleash the ultimate performance of smart systems of the future.
| Champ | Valeur |
|---|---|
| Secteur | Semiconductor Manufacturing |
| Taille | 11-50 employees |
| Siège social | Santa Clara |
| Type d’organisation | Privately Held |
| Fondée en | 2021 |
| Offres sur Jobsy | 5 |
| Voir la page |
Join the leading chiplet startup! As an Eliyan Staff Design Engineer, you will be working at a fast-paced early-stage startup creating technologies that fuel tomorrow's chiplet-based systems with best-in-class power, area, manufacturability, and design flexibility. In this role you will lead the verification of Serdes. You will be developing state-of-the-art testbenches and unit/chip level test cases for best-in-class PHYs. You will own verification of TX/RX equalization and CDR. This is a hands-on technical leadership role. You'll define PHY verification architecture, write UVM/SV testbenches, and make sure that designs are bug free. You will work with a cross-functional team of experts. We offer a fun work environment with excellent benefits. ONSITE M-F.
Key Responsibilities:
- Develop and execute verification plans for Serdes, other PHYs, DSP blocks, TX/RX equalization and CDR.
- Create and maintain SystemVerilog/UVM-based verification environments
- Write and debug SystemVerilog/UVM compliant test cases for block and chip level
- Maintain regression environments
- Collaborate with design team to ensure design quality
- Develop, maintain, and track various test plan items and progress towards RTL freeze
- Stay up to date with industry trends, emerging technologies and progress in standards’ bodies
- Integration of 3rd party VIPs and coordinate feature/bug tracking requests
- As a technical leader, mentor junior verification engineers
- GLS simulation for functional verification and power calculations
Required Qualifications:
- BS + 7 years of verification experience with 4+ years in PHY or high-speed interfaces
- Deep verification expertise in SerDes/PCIePHY, TX/RX equalization, CDR
- Strong expertise in UVM/SystemVerilog, test environment and assertion coding
- Experience in verifying mixed signal IPs as well as integration of VIPs
Preferred Qualifications:
- 10+ years with demonstrated verification technical leadership
- Experience with Formal verification with Jasper Gold or vc-formal
- Experience with GLS simulations
- Python/Perl/Tcl scripting for design verification
- Proficiency in 3rd party tools for regression management and coverage analysis
Journal
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