R&D Engineering, Engineer
Vancouver, BCSynopsys
Candidates need a bachelor's degree in computer science or engineering and 0 to 2 years of software development experience. They need solid C++ skills and understanding of data structures and algorithms.
Use questioning techniques, Team building, Communication skills, Computer science, Software development, C++
AMS Design Verification Engineer
Mississauga, ONSynopsys
5+ ansSynopsys needs candidates with a degree in electrical or computer engineering and strong knowledge of analog and mixed-signal circuits. Candidates should know SystemVerilog and UVM, have used AMS simulation tools, and be comfortable scripting in Python, Perl or shell.
HSPICE, XA, CustomSim, VCS, SystemVerilog, UVM
Principal Analog Mixed Signal Designer - 19497
Mississauga, ONSynopsys
5+ ansCandidates need a PhD with 5+ years or a Master's with 8+ years of hands-on analog IC design experience. Strong CMOS skills, detailed SerDes sub-circuit design experience and SPICE simulation expertise are required.
SPICE simulators, Verilog-A, schematic entry tools, physical layout tools, MATLAB, Python
IT Reliability, Site Associate
CanadaSynopsys
Candidates need a bachelor's degree in a related field, hands-on experience across Linux and Windows, and scripting ability in Bash, PowerShell or Python. Strong methodical troubleshooting and clear English communication are required.
Citrix, Linux, Windows, PowerShell, Bash, Python
Sr Manager or Principal Engineer for Firmware Development - 19315
Markham, ONSynopsys
10+ ansCandidates need a Bachelor's, Master's or PhD in computer or electrical engineering, or equivalent experience, with 10+ years in a related field. They need strong skills in digital logic and firmware development, proficiency in C, Verilog and SystemVerilog/UVM, and experience leading complex projects.
Verilog, UVM, C, Python, Perl, Bash
R&D Engineering, Sr Staff Engineer
Nepean, ONSynopsys
8+ ansCandidates need a bachelor's degree in a related field or equivalent experience, typically 8+ years building production enterprise web applications, and deep PANN stack experience. They also need strong database, cloud, container and CI/CD skills, practical AI experience, and strong communication abilities.
PostgreSQL, Angular, NestJS, Node.js, Prisma, Docker
ASIC Digital Design, Sr Staff Engineer-19314
Markham, ONSynopsys
8+ ansCandidates need a BS or MS in electronics or electrical engineering with 8+ years of digital verification experience in VMM or UVM. Strong Verilog and SystemVerilog testbench skills, debugging ability, and familiarity with Python or Perl are required.
Verilog, SystemVerilog, UVM, VMM, Jira, Confluence
Hardware Engineering, Staff Engineer- 19028
Nepean, ONSynopsys
Candidates need proven experience with high-speed interface signaling, signal and power integrity analysis, and EDA tools such as HFSS, Ansys, HSPICE, Raptor and ADS. They also need strong communication skills and board-level and on-chip IO design knowledge.
HFSS, Ansys, HSPICE, Raptor, ADS
Principal Analog Design Engineer-19318
Markham, ONSynopsys
6+ ansCandidates need a PhD with 6+ years or a Master's with 8+ years of analog and mixed-signal IC design experience, including FinFET circuit design. Strong transistor-level CMOS and SPICE simulation skills are required.
Spectre, HSPICE, Verilog-A, schematic entry tools, Python, Perl
R&D Engineering, Staff Engineer
Ottawa, ONSynopsys
7+ ansCandidates need 7-8+ years of experience with a bachelor's degree, 5-6+ with a master's, or 3-4+ with a PhD, in an engineering or computer science field. They need strong skills in CAD or simulation infrastructure, scripting in Python, Tcl or Shell, and Linux environments.
Synopsys EDA design suite, Linux, Python, Tcl, Shell
Analog Design, Architect - 18618
Mississauga, ONSynopsys
10+ ansCandidates need a PhD with 10+ years or MSc with 12+ years of SerDes or high-speed analog design experience. Synopsys expects silicon-proven TX, RX and clock circuit work, transistor-level CMOS and FinFET layout skills, and some leadership of small teams.
SPICE, Verilog-A, TCL, Perl, C, Python
CAD Software Engineer, Principal-18736
Nepean, ONSynopsys
10+ ansSynopsys needs candidates with an MS or PhD in Computer Science or Electrical Engineering and at least 10 years of industry experience. They should be strong in Python, Perl, TCL, UNIX/Linux, Git, and Perforce, and have hands-on experience with Custom Compiler/Virtuoso.
Custom Compiler, Virtuoso, Git, Perforce, UNIX, Linux
Staff Application Engineer
Mississauga, ONSynopsys
7+ ansCandidates need a bachelor's degree in electrical and electronics engineering with 7+ years of applications, verification or emulation experience, or a master's with 5+ years. They need hands-on emulation platform experience, HDL and UVM skills, and scripting in Python, Perl or TCL.
Synopsys ZeBu, Mentor Veloce, Cadence Palladium, Verilog, SystemVerilog, VHDL
Validation / Verification Eng, Staff Engineer
Nepean, ONSynopsys
6+ ansCandidates need a Bachelor's or Master's in electrical or electronics engineering (or equivalent experience), 6-8+ years of high-speed hardware validation, and expert Cadence Allegro skills. They also need strong signal integrity knowledge and experience with oscilloscopes, logic analyzers and network analyzers.
Cadence Allegro, oscilloscope, logic analyzer, protocol analyzer, vector network analyzer, spectrum analyzer
ASIC Physical Design, Sr Staff Engineer - 16724
Nepean, ONSynopsys
9+ ansCandidates need 9+ years of ASIC physical design experience on complex SoC or test chip projects at advanced nodes. They must know the full physical design flow and tools such as Design Compiler, PrimeTime, IC Compiler II, Calibre and RedHawk, and must be authorized to work in the USA.
Design Compiler, PrimeTime, IC Compiler II, ICV, Calibre, RedHawk
Analog Design, Sr Staff Engineer - 18144
Kanata, ONSynopsys
8+ ansCandidates need a master's degree with 8+ years or a PhD with 6+ years of analog circuit design experience. Experience with op-amps, current mirrors and bandgaps is required, and SERDES or DDR knowledge is strongly desired.
CAD tools for analog design
ASIC Digital Design, Architect
Markham, ONSynopsys
10+ ansCandidates need a master's degree or equivalent experience and 10+ years of digital ASIC design, ideally in high-speed or mixed-signal work. They need strong Verilog or VHDL skills, clock domain crossing knowledge, synthesis and DFT experience, and experience working with verification teams.
Verilog, VHDL, synthesis tools, DFT tools
Senior Staff Applications Engineer (Electronics Thermal Management)
CanadaSynopsys
4+ ansCandidates need an MS in Mechanical Engineering or related field with 6+ years in engineering software, a BS with 8+ years, or a PhD with 3+ years. They must have 4+ years of customer-facing application engineering and strong CFD and thermal skills, plus hands-on Ansys experience.
Ansys Fluent, Ansys Icepak, Ansys Mechanical
Sr. Staff AI Full Stack Engineer
Mississauga, ONSynopsys
Candidates need advanced Python skills for full stack work, cloud and container experience, working knowledge of generative AI and LLM applications, and strong distributed systems and API design. Leadership and mentoring ability is also required.
Python, Docker, Kubernetes, AWS, GCP, Azure
Analog Design, Principal Engineer- 18339
Markham, ONSynopsys
8+ ansCandidates need 8+ years of CMOS analog or mixed-signal design experience and strong expertise in transistor-level and SerDes circuits. Hands-on FinFET layout, SPICE and scripting skills, and knowledge of reliability and ESD design are also required.
SPICE simulators, EDA tools, Python, TCL
R&D Engineering , Sr Engineer
Vancouver, BCSynopsys
2+ ansCandidates need a bachelor's degree in a technical field and 2+ years of software development. They need strong C++, data structures and geometric algorithm skills, with meshing experience a strong plus.
C++
St Staff R&D Engineer
Waterloo, ONSynopsys
5+ ansCandidates need a bachelor's or master's degree in computer science or a related field, plus 5+ years of production software experience. Strong skills in C#, .NET, Python and Angular, and the ability to design software frameworks, are required.
Angular, Python, C#, React
Principal Physical Design Methodology Engineer
Markham, ONSynopsys
10+ ansCandidates need a Bachelor's or Master's in Electrical or Computer Engineering and 10+ years of ASIC digital implementation experience. Deep expertise with Fusion Compiler or ICC2, high-speed IP experience, and Tcl and Python scripting are required.
Fusion Compiler, ICC2, Innovus, PrimeTime, PrimePower, Tcl
R&D Engineering, Staff Engineer
Vancouver, BCSynopsys
5+ ansCandidates need a bachelor's degree in a technical field and 5+ years of software development (3+ with a master's or PhD). Strong C++ skills, performance optimization and GPU experience such as CUDA or OpenCL are needed.
C++, CUDA, OpenCL