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RTL Design Engineer – PCIe

@ Yochana

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Canada

Contrat
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SIGNAUX

En bref

Yochana is hiring a contract RTL Design Engineer focused on PCIe to write and implement digital logic in Verilog and SystemVerilog. The work covers micro-architecture development, RTL implementation, and verification of PCIe Gen3/Gen4/Gen5 protocols.

Responsabilités :

  • RTL design in Verilog/SystemVerilog
  • PCIe Gen3/Gen4/Gen5 protocol verification
  • Micro-architecture development and RTL implementation
  • Debugging and problem-solving

Résumé des exigences :

  • Hands-on RTL design in Verilog/SystemVerilog
  • Digital design fundamentals (FSM, CDC, reset, low-power)
  • Knowledge of synthesis constraints and timing
  • Familiarity with Lint, CDC, STA and low-power verification
  • Bachelor's or Master's in ECE, EEE or related field preferred

Outils et compétences

VerilogSystemVerilog
Source et dates

Type de source non vérifié · apify-linkedin

Date publiée par l’employeur
2026-11-10
Première détection par notre source
2026-11-11
Mise à jour du dossier source
2026-11-11

Ces dates décrivent le dossier source, pas une vérification en direct du recrutement. Consultez l’offre originale.

Détails du poste

DomaineGénie
Milieu de travailBureau
PositionSurtout assis
Exigences physiquesphysique faible · ordinateur élevé
FormationBaccalauréat (préféré), Maîtrise (préféré)
Domaines d’étudesElectrical and Computer Engineering, Electrical and Electronics Engineering, Electronics Engineering

Résumé et détails rédigés par l’IA à partir de l’offre; l’offre de l’employeur fait foi.

Postuler
ChampValeur
Offres sur Jobsy14
Description

Key Responsibilities & Required Skills
Strong hands-on experience in RTL Design using Verilog/SystemVerilog.
Hands-on experience in verification of PCIe Gen3/Gen4/Gen5 protocols.
Good understanding of digital design fundamentals, including FSM design, pipelining, CDC, reset architecture, synchronizers and low-power design concepts.
Experience in micro-architecture development and RTL implementation.
Knowledge of synthesis constraints and timing concepts.
Familiarity with Lint, CDC, STA and low-power verification methodologies.
Strong debugging and problem-solving skills.
Preferred Qualifications
Bachelor's or Master's degree in ECE, EEE, Electronics or a related engineering discipline.
Relevant experience in RTL Design and/or PCIe Design Verification.
Good understanding of ASIC design and verification flows.

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