Senior ASIC RTL Design Engineer, AI Networking IP
Ottawa, ONTemps plein
AM
Advanced Micro Devices, Inc
Candidates need a Bachelor's or Master's in computer or electrical engineering, and strong Verilog or SystemVerilog RTL design skills. Experience delivering ASIC or FPGA products, plus networking or high-speed interface knowledge, is preferred.
Verilog, SystemVerilog, Synopsys tools, Cadence tools, Siemens (Mentor) tools, Python