Analog Design, Principal Engineer- 18339
Markham, ONSynopsys
8+ ansCandidates need 8+ years of CMOS analog or mixed-signal design experience and strong expertise in transistor-level and SerDes circuits. Hands-on FinFET layout, SPICE and scripting skills, and knowledge of reliability and ESD design are also required.
SPICE simulators, EDA tools, Python, TCL
Analog Design, Manager - 18463
Kanata, ONSynopsys
8+ ans2+ gestionCandidates need an M.A.Sc. with 8+ years or a PhD with 6+ years of analog or mixed-signal IC design experience, plus 2+ years of people management. They must have deep Multi-Gbps SerDes expertise, transistor-level design skills, and experience with SPICE, Verilog-A and layout.
SPICE, Verilog-A, Industry-standard simulation tools
Pre-Silicon Signoff Lead
Mississauga, ONSynopsys
10+ ansCandidates need an MSc or PhD in electrical or computer engineering and 10+ years of industry experience. They need deep knowledge of PCIe and Ethernet, SystemVerilog, UVM and scripting, plus proven leadership and mentoring skills.
SystemVerilog, UVM, Python, TCL, Perl, C++