Principal Analog Design Engineer-19318
Markham, ONS
Synopsys
6+ ansCandidates need a PhD with 6+ years or a Master's with 8+ years of analog and mixed-signal IC design experience, including FinFET circuit design. Strong transistor-level CMOS and SPICE simulation skills are required.
Spectre, HSPICE, Verilog-A, schematic entry tools, Python, Perl
Analog Design, Architect - 18618
Mississauga, ONS
Synopsys
10+ ansCandidates need a PhD with 10+ years or MSc with 12+ years of SerDes or high-speed analog design experience. Synopsys expects silicon-proven TX, RX and clock circuit work, transistor-level CMOS and FinFET layout skills, and some leadership of small teams.
SPICE, Verilog-A, TCL, Perl, C, Python