Staff Design Verification Engineer
Toronto, ONTalentlab
9+ ansCandidates need a Bachelor's or Master's in computer science, electrical engineering or a related field, plus at least 9 years of ASIC design verification experience. Strong SystemVerilog and UVM skills and advanced debugging are required.
SystemVerilog, UVM, EDA tools
Senior Design Verification Engineer
Toronto, ONTalentlab
3+ ansTalentlab needs candidates with 3 to 8 years of design verification experience and strong SystemVerilog and UVM skills. Experience with SerDes, DSP or mixed-signal designs is needed, and Ethernet and PCIe knowledge is a strong plus.
SystemVerilog, UVM, Python, Perl, C/C++, GNU Make
Staff Physical Design Engineer
Toronto, ONTalentlab
5+ ansCandidates need 5+ years of physical design experience on digital ASICs, including advanced nodes like TSMC N5, N4P or N3. They must know industry EDA tools, PnR, timing analysis and physical verification, and be strong in TCL, Python or Perl.
Synopsys ICC2, Cadence Innovus, Calibre, PrimeTime, RedHawk, TCL
Analog IC Design Engineer
Toronto, ONTalentlab
5+ ansCandidates need an MSc or PhD in electrical engineering or a related field and 5+ years of analog IC design experience, preferably silicon-proven. They need hands-on advanced CMOS experience, SPICE and Verilog-A simulation skills, and EDA tool proficiency.
SPICE, Verilog-A, EDA tools