Digital - Staff Digital Design Engineer - PHY
CanadaSur placeTemps plein
E
Eliyan
8+ ansEliyan needs 8+ years of digital frontend design with 4+ years in PHY or high-speed interfaces, and 3+ tapeouts as design lead at 7nm or below. Candidates need expert SystemVerilog, synthesis, CDC and UCIe or DDR/SerDes knowledge.
SystemVerilog, Synopsys Design Compiler, Synopsys Fusion Compiler, Cadence Genus, UPF, SDC