Senior ASIC RTL Design Engineer, AI Networking IP
Ottawa, ONAMD, Inc.
Candidates need proven RTL design experience in Verilog or SystemVerilog, ASIC or FPGA delivery experience, and a bachelor's or master's degree in computer or electrical engineering. Networking or high-speed interface knowledge, such as Ethernet or PCIe, is preferred.
Verilog, SystemVerilog, Synopsys tools, Cadence tools, Siemens (Mentor) tools, Python
STA/Constraints Engineer
Vancouver, BCAMD, Inc.
Candidates need industry experience in STA, constraints and timing signoff, and expert use of Synopsys PrimeTime and GCA (ICC2 or Fusion Compiler desired). Scripting in Perl, TCL, Shell or Python and Verilog RTL experience are valued.
ICC2, Verilog
Sr. Manager - RTL Design Manager
Markham, ONAMD, Inc.
AMD needs a leader with experience managing IP or RTL design teams and strong Verilog/SystemVerilog skills. Candidates should know RTL microarchitecture, ASIC verification flows and on-chip protocols such as AXI and AHB, and hold a bachelor's degree in an engineering or computer discipline.
Verilog, SystemVerilog
System Validation Engineer – Data Center GPU
Markham, ONAMD, Inc.
Candidates need experience in system, platform, firmware, server, GPU or SoC validation, plus knowledge of PLDM, Redfish and firmware security testing. Scripting skills, Linux and Windows experience, and a bachelor's or master's degree in electrical or computer engineering (or equivalent) are required.
Linux, Windows
Principal ASIC Design Engineer
Markham, ONAMD, Inc.
Candidates need a track record of leading ASIC or silicon designs through multiple product tape-outs, plus deep RTL and microarchitecture experience. Strong communication skills and the ability to lead technical reviews are also required.
Verilog, SystemVerilog, Python, Perl, Tcl
Senior Firmware Engineer
Markham, ONAMD, Inc.
Candidates need extensive experience with microcontrollers and embedded C or assembly, strong low-level hardware and firmware interface knowledge, and a bachelor's or master's degree in electronics, computer engineering or another applied science.
Git, GitHub Actions, Python, RTOS, emulation platforms, RTL simulation tools
Design Verification Lead
Markham, ONAMD, Inc.
Candidates need a bachelor's or master's degree in electrical or computer engineering, computer science or a related field, plus UVM and SystemVerilog experience and knowledge of high-speed protocols such as PCIe, CXL or Ethernet. Scripting in Python or Perl and technical leadership skills are also needed.
SystemVerilog, Verilog, UVM, Python, Perl