SoC Design Lead, Microarchitecture and Design Methodology
Markham, ONAMD, Inc.
Candidates need a strong foundation in computer architecture and digital design, along with static timing analysis, clock and power optimization knowledge. Experience with Verilog or SystemVerilog, and UVM preferred, plus strong communication and teamwork skills.
Verilog, SystemVerilog, UVM
Silicon Design Verification Engineer
Markham, ONAMD, Inc.
Candidates need a Bachelor's or Master's in Computer or Electrical Engineering, knowledge of digital design and computer architecture, and hands-on SystemVerilog, UVM and C++ or Python experience. Prior verification work and PCIe or AXI protocol knowledge are assets.
UVM, C++, Python, Formal verification tools
RTL Design Engineer
Markham, ONAMD, Inc.
Candidates need experience with I/O protocols such as USB, PCIe and CXL, plus RTL design for multi-clock, high-frequency, low-power designs. A bachelor's or master's degree in electrical engineering or equivalent is preferred.
Python, Perl
Lead Physical Design Engineer, Place & Route
Markham, ONAMD, Inc.
Candidates need hands-on place-and-route experience on complex or advanced-node designs, proficiency with Synopsys Fusion Compiler, Cadence and Siemens EDA tools, and scripting in TCL, Perl or Shell. A bachelor's or master's degree in electrical or computer engineering is preferred.
Synopsys Fusion Compiler, Cadence, Siemens EDA, TCL, Perl, Shell
Physical Design Engineer
Markham, ONAMD, Inc.
Candidates need a bachelor's degree in an electrical, electronics or computer engineering discipline and deep experience in ASIC physical design implementation and signoff. They also need hands-on skill with industry EDA tools and power, performance and area optimization.
Synopsys ICC2, Cadence Innovus, PrimeTime, Spyglass, RedHawk, Calibre
Static Timing Analysis / Full Chip Timing Engineer
Markham, ONAMD, Inc.
Candidates need a BS, MS or PhD in Electrical Engineering, Computer Engineering or a related field. Full-chip timing experience is preferred, along with the ability to explain complex timing data to technical and management audiences.
DFT, Root cause analysis, Collaboration, Communication skills, Electrical engineering, Computer engineering
STA/Constraints Engineer
Vancouver, BCAMD, Inc.
Candidates need industry experience in STA, constraints and timing signoff, and expert use of Synopsys PrimeTime and GCA (ICC2 or Fusion Compiler desired). Scripting in Perl, TCL, Shell or Python and Verilog RTL experience are valued.
ICC2, Verilog