FY27 Intern - Design Verification Engineering Internship - Canada (16 months)
Toronto, ONQualcomm Canada ULC
1+ ansCandidates need to be enrolled in a bachelor's program in electrical, computer or engineering science, or a related field, with an expected graduation of November 2028 or later. They need at least one year of academic programming experience in C, C++ or Python, and are preferred with Verilog/SystemVerilog and verification methodology knowledge.
Synopsys VCS, Verdi, SystemVerilog, Verilog, UVM
Analog Engineer, Staff
Toronto, ONQualcomm Canada ULC
4+ ansCandidates need a bachelor's, master's or PhD in electrical engineering with analog or mixed-signal CMOS design experience and several years of ASIC design or verification work. Experience with circuit design tools, transistor-level design, layout optimization and silicon-proven analog blocks is required.
Cadence ADE, MATLAB, SPICE, Verilog-A, Verilog, VHDL