FY27 Intern - Digital Design Engineering Internship - Canada (16 months)
Toronto, ONQualcomm Canada ULC
1+ ansCandidates need to be enrolled in a bachelor's program in electrical or computer engineering, computer science or a related field, with graduation in November 2028 or later. Experience with Verilog or SystemVerilog, RTL design and at least one year of programming in C, C++ or Python is required, with FPGA or tapeout experience as a plus.
Verilog, SystemVerilog, FPGA, EDA tools
Analog Engineer, Staff
Toronto, ONQualcomm Canada ULC
4+ ansCandidates need a bachelor's, master's or PhD in electrical engineering with analog or mixed-signal CMOS design experience and several years of ASIC design or verification work. Experience with circuit design tools, transistor-level design, layout optimization and silicon-proven analog blocks is required.
Cadence ADE, MATLAB, SPICE, Verilog-A, Verilog, VHDL
FY27 Intern - QDSP Hardware Physical Design Internship - Canada (12 or 16 months)
Markham, ONQualcomm Canada ULC
1+ ansCandidates need to be in study toward a bachelor's or master's degree in electrical, computer or a related engineering or science field, with 1+ years of academic programming experience. VLSI project experience and skill in TCL, Perl or Python are desirable.
EDA tools
Cross-Functional Engineer, Staff
Toronto, ON +1Qualcomm Canada ULC
4+ ansCandidates need a bachelor's, master's or PhD in Electrical Engineering with analog or mixed-signal chip design experience and several years of ASIC design or verification work. They also need strong high-speed SerDes knowledge, SystemVerilog and EDA tool skills.
Cadence, SPICE, MATLAB, Verilog, VHDL, SystemVerilog
Analog Engineer, Principal
Toronto, ONQualcomm Canada ULC
8+ ansCandidates need a Master's or PhD in electrical engineering (or a Bachelor's with 2+ years of analog or mixed-signal design), plus 8+ years of ASIC design or related work and silicon-proven analog circuit experience in advanced CMOS. Strong skills in Cadence, SPICE, MATLAB or Verilog-A are expected.
Cadence ADE, MATLAB, SPICE, Verilog-A
Staff Engineer, Physical Design/Implementation
Toronto, ONQualcomm Canada ULC
3+ ansCandidates need a Master's degree with 3+ years or a Bachelor's with 4+ years of ASIC physical design experience. They need hands-on skill with industry chip design tools and strong knowledge of timing, power and clocking.
Cadence Innovus, Synopsys ICC2
Physical Design Engineer, Staff
Toronto, ONQualcomm Canada ULC
7+ ansCandidates need 7+ years of physical design experience and a Bachelor's in Electrical or Computer Engineering or equivalent. Low-power, SoC and advanced technology node experience are desired, along with strong analytical, scripting and collaboration skills.
EDA tools
Engineer
Markham, ONQualcomm Canada ULC
1+ ansCandidates need a bachelor's degree in engineering or a related field, plus 6 months to 2 years of experience in chip design, VLSI or digital design, including internships. They should understand digital logic and timing, know basic physical design steps, and have scripting skills in Python, Tcl, Perl or Shell.
Verilog, SystemVerilog, EDA tools
FY27 Intern - Camera Design Engineering Internship - Canada (12 or 16 months)
Vancouver, BCQualcomm Canada ULC
1+ ansCandidates need to be enrolled toward a bachelor's degree in electrical, computer or a related engineering or science field. They need experience in Tcl, Perl, Python and SystemVerilog, plus academic or project VLSI experience as an asset.
Verilog, Tcl, Perl, Python, EDA tools