Emplois “SystemVerilog UVM” au Canada – Page 2

Aucun filtre correspondant. Essayez un autre nom.

Résultats

• 25j

  Summer 2027 Long Term ASIC Verification Engineering Intern/ Co-Op

  Ottawa, ON

  AI

  AMD, Inc.

  Candidates need to be 3rd or 4th year Computer Engineering or Computer Science students with digital design knowledge, object-oriented coding skills, and experience with SystemVerilog, C or C++. Python, Perl or other scripting experience and AI tools experience are assets, and valid work authorization is required.

  SystemVerilog, UVM, C, C++, Python, Perl

  27j

  SoC Design Lead, Microarchitecture and Design Methodology

  Markham, ON

  Temps plein

  AI

  AMD, Inc.

  Candidates need a strong foundation in computer architecture and digital design, along with static timing analysis, clock and power optimization knowledge. Experience with Verilog or SystemVerilog, and UVM preferred, plus strong communication and teamwork skills.

  Verilog, SystemVerilog, UVM

  27j

  Design Verification Lead

  Markham, ON

  Temps plein

  AI

  AMD, Inc.

  Candidates need a bachelor's or master's degree in electrical or computer engineering, computer science or a related field, plus UVM and SystemVerilog experience and knowledge of high-speed protocols such as PCIe, CXL or Ethernet. Scripting in Python or Perl and technical leadership skills are also needed.

  SystemVerilog, Verilog, UVM, Python, Perl

• 26j

  Co-op ASIC Digital Verification Engineer

  Ottawa, ON

  

  SiTime Corporation: SiTime Corporation (Nasdaq: SITM), the market leader in silicon MEMS timing, is an analog and semiconductor company that is revolutionizing the…

  Candidates need good academic standing, object-oriented coding skills and strong problem-solving ability. Knowledge of Verilog, SystemVerilog, UVM, Python or Tcl is an asset, and English proficiency is required.

  Verilog, SystemVerilog, UVM, Python, Tcl

  26j

  ASIC Digital Verification Engineer

  Ottawa, ON

  

  SiTime Corporation: SiTime Corporation (Nasdaq: SITM), the market leader in silicon MEMS timing, is an analog and semiconductor company that is revolutionizing the…

  Candidates need knowledge of chip specifications and verification plans, plus SystemVerilog and UVM for digital verification. Experience with Synopsys or Cadence simulators, SystemVerilog assertions, functional and code coverage, and working in Unix/Linux is also needed.

  SystemVerilog, UVM, Unix, Linux

• 26j

  Staff Design Verification Engineer

  Toronto, ON

  T

  Talentlab

  9+ ansCandidates need a Bachelor's or Master's in computer science, electrical engineering or a related field, plus at least 9 years of ASIC design verification experience. Strong SystemVerilog and UVM skills and advanced debugging are required.

  SystemVerilog, UVM, EDA tools

  26j

  Senior Design Verification Engineer

  Toronto, ON

  T

  Talentlab

  3+ ansTalentlab needs candidates with 3 to 8 years of design verification experience and strong SystemVerilog and UVM skills. Experience with SerDes, DSP or mixed-signal designs is needed, and Ethernet and PCIe knowledge is a strong plus.

  SystemVerilog, UVM, Python, Perl, C/C++, GNU Make

  26j

  Senior ASIC Verification Engineer

  Ottawa, ON

  Hybride

  T

  Talentlab

  Candidates need an engineering degree, proven digital verification experience, and knowledge of formal verification and functional coverage. They should also be proficient in a programming language such as Python or C/C++ and be based in Ottawa.

  SystemVerilog, UVM, Python, C++, SystemC, Make

• 27j

  Design Verification Engineer Intern (Toronto)

  Toronto, ON

  AL

  Astera Labs Early Career - North America 2027

  Candidates need to be pursuing a bachelor's or master's degree in electrical, computer engineering or computer science. They need coding skills in SystemVerilog, C/C++ or Python, Linux and Git familiarity, and strong debugging ability.

  VCS, Verdi, DVE

• 28j

  Design Verification Lead

  Markham, ON

  Temps plein

  AM

  Advanced Micro Devices, Inc

  Candidates need a Bachelor's or Master's degree in an electrical, computer or related engineering field, strong UVM and SystemVerilog skills, and experience verifying high-speed protocols such as PCIe, CXL or Ethernet. Technical leadership, mentoring and scripting in Python or Perl are preferred.

  SystemVerilog, Verilog, UVM, Python, Perl

  1 mois

  Summer 2027 Long Term ASIC Verification Engineering Intern/ Co-Op

  Ottawa, ON

  AM

  Advanced Micro Devices, Inc

  Candidates need to be 3rd or 4th year Computer Engineering or Computer Science students with digital design knowledge, object-oriented coding skills, and experience with SystemVerilog, C or C++. Experience with AI tools is required, and Python, Perl or other scripting languages are an asset.

  SystemVerilog, UVM, C++, Python, Perl

  1 mois

  SoC Design Lead, Microarchitecture and Design Methodology

  Markham, ON

  Temps plein

  AM

  Advanced Micro Devices, Inc

  Candidates need a strong foundation in computer architecture and digital design, with knowledge of static timing analysis, clocks and power optimization. Verilog or SystemVerilog experience, with UVM preferred, and strong communication and teamwork skills are needed.

  Verilog, SystemVerilog, UVM

• 1 mois

  Principal Digital Verification Engineer

  Nepean, ON

  S

  Synopsys

  12+ ansSynopsys candidates need 12+ years of verification experience with a BSc, 10+ years with an MSc, or 8+ years with a PhD. They need deep SystemVerilog and UVM skills, simulation and waveform debugging, C knowledge, assertion-based verification, and Linux scripting. Experience with LPDDR5/5X or LPDDR6 and emulation platforms is a plus.

  SystemVerilog, UVM, waveform debugger, Linux, source control, emulation platform

  1 mois

  ASIC Digital Design, Principal Engineer-18731

  Mississauga, ON

  S

  Synopsys

  Candidates need extensive mixed-signal ASIC or IP verification experience, strong PCIe and PCIe PHY knowledge, and hands-on SystemVerilog and UVM skills. Strong debugging and mentoring abilities are also required.

  SystemVerilog, UVM

  1 mois

  ASIC Digital Verification, Sr. Manager

  Mississauga, ON

  S

  Synopsys

  15+ ansCandidates need a BS or MS in EE, EC or VLSI with 15+ years of IP or SoC verification experience, and strong team leadership. They must know Verilog, SystemVerilog and UVM, and Perl or Python automation. PCIe and Ethernet knowledge is an asset.

  Verilog, SystemVerilog, UVM, Perl, Python

• 1 mois

  Staff ASIC Verification Engineer, Low Power AI

  Markham, ON

  Sur place

  

  Qualcomm Canada ULC

  4+ ansQualcomm Canada ULC needs candidates with a relevant degree and 4+ years of ASIC work (3+ with a master's, 2+ with a PhD). Expert knowledge of Verilog, VHDL and SystemVerilog UVM is required, plus solid C skills.

  SystemVerilog, UVM, Verilog, VHDL, SystemC, Perl

  1 mois

  Digital Design Verification Engineer, Staff

  Toronto, ON

  Sur place

  

  Qualcomm Canada ULC

  4+ ansCandidates need a bachelor's degree in a science or engineering field with 4+ years of ASIC design or verification experience, or an equivalent master's or PhD with less experience. Strong SystemVerilog, UVM and scripting skills and proven leadership and communication are required.

  Verilog, SystemVerilog, UVM, Python, Perl, C/C++

  1 mois

  Design Verification Engineer — Memory Subsystem (Vancouver)

  Vancouver, BC

  Sur place

  

  Qualcomm Canada ULC

  3+ ansCandidates need a bachelor's or master's degree in an engineering or computer science field and 3 to 10 years of chip or subsystem verification experience. Hands-on skill with Verilog, SystemVerilog, UVM and assertions is required, and knowledge of memory standards such as DDR, LPDDR and HBM is preferred.

  Verilog, SystemVerilog, UVM, SystemVerilog Assertions, waveform viewers

  1 mois

  Senior ASIC Design Verification Engineer, Compute DSP/AI Processors (multiple levels)

  Markham, ON

  Sur place

  

  Qualcomm Canada ULC

  4+ ansCandidates need an engineering degree and, for senior roles, several years of ASIC design or verification experience. Strong skills in UVM, SystemVerilog, digital logic and scripting in Python or CShell are expected, along with good problem solving and communication.

  SystemVerilog, UVM, Python, CShell

• 1 mois

  Principal Design Verification Engineer

  Toronto, ON

  

  indie

  7+ ansCandidates need a BSEE, BSCE or BSCS and 7+ years of design verification experience. Required skills include constrained random verification with SystemVerilog and UVM, coverage-driven verification, and strong programming in C/C++ with Python, Tcl or Perl scripting.

  SystemVerilog, UVM, C, C++, Python, Tcl

• 1 mois

  Senior I/O Chiplet Verification Engineer

  Ottawa, ON

  Temps plein

  

  BTA Design Services: specializes in ASIC and FPGA design and verification services, custom IP development, embedded software, and DevOps capabilities creation.

  10+ ansCandidates need 10 or more years of hands-on ASIC verification experience through tape-out sign-off, strong SystemVerilog and UVM skills, and experience with high-speed interfaces or die-to-die interconnect. Scripting, regression automation and clear written communication are essential.

  SystemVerilog, UVM, UPF

  1 mois

  Senior FPGA Design Engineer

  Ottawa, ON

  Temps plein

  

  BTA Design Services: specializes in ASIC and FPGA design and verification services, custom IP development, embedded software, and DevOps capabilities creation.

  10+ ansCandidates need about 10 to 15 years of hands-on FPGA design experience and strong current SystemVerilog skills. They must handle clock domain crossings, configure synthesis tools, write SDC constraints, and analyze synthesis reports, and be available to work on-site in Ottawa.

  SystemVerilog, SDC

• 1 mois

  Senior Hardware Engineer

  Burnaby, BC

  108k–153k $/anTemps plein

  

  LMI Technologies

  5+ ansCandidates need a bachelor's degree in electrical engineering and at least five years designing and testing digital logic such as FPGAs or ASICs. Hands-on experience with VHDL or Verilog, high-speed interfaces and self-verifying simulation environments is required.

  Vivado, Chipscope, Logic analyzers, Oscilloscopes, Xilinx IP, Intel FPGA

• 1 mois

  FPGA Engineer

  Ottawa, ON

  105k–145k $/anTemps plein

  

  Q-Block Computing: Imagine instruments precise enough to probe this reality—to ask whether the cosmos operates according to Nature’s own algorithms.

  4+ ansCandidates need a related engineering degree, 4+ years of professional FPGA design and verification experience, and hands-on work with Vivado, Quartus or Lattice toolchains. They also need strong high-speed digital design skills and proficiency with oscilloscopes, logic analyzers and signal generators.

  Xilinx Vivado, Intel Quartus, Lattice toolchain, oscilloscope, logic analyzer, signal generator

11 entreprises