Emplois “logic synthesis tools” au Canada – Page 2

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• 21j

  Sr. Staff Physical Design Engineer

  Vancouver, BC

  Temps plein

  AM

  Advanced Micro Devices, Inc

  AMD needs candidates with strong physical design experience for high-performance semiconductors, including timing closure and signoff. Candidates should know tools such as ICC2, Fusion Compiler, PrimeTime, Calibre and Innovus, and be proficient in Python and TCL.

  Synopsys ICC2, Synopsys ICC, Fusion Compiler, PrimeTime, StarRC, Mentor Graphics Calibre

  1 mois

  Short Term 2027 Data Analyst Intern/Co-Op

  Markham, ON

  AM

  Advanced Micro Devices, Inc

  Candidates need to be enrolled in a Canadian university undergraduate program in data analytics, data engineering, computer or electrical engineering, computer science or a related field. Skills in Python, SQL, R, Java, Tableau, Power BI and cloud data platforms are strongly encouraged.

  Python, SQL, R, Java, Power BI, Kubernetes

  1 mois

  SoC Design Lead, Microarchitecture and Design Methodology

  Markham, ON

  Temps plein

  AM

  Advanced Micro Devices, Inc

  AMD needs candidates with a strong foundation in digital design, computer architecture, static timing analysis and power optimization. Strong written and verbal communication, analytical skills and a degree in computer, electrical engineering or a related field are preferred.

  Verilog, SystemVerilog, UVM

  1 mois

  SoC Lead Engineer – LEC & Low Power Signoff

  Markham, ON

  Temps plein

  AM

  Advanced Micro Devices, Inc

  Advanced Micro Devices needs candidates with proven SoC implementation and tapeout experience, deep knowledge of equivalence checking and low power verification, and hands-on use of industry EDA tools. Strong scripting, debugging, leadership and communication skills are also required, along with a BS or MS in Electrical Engineering, ECE, EEE or a related field.

  Synopsys Formality, Cadence Conformal, Synopsys VC-LP, Cadence Conformal Low Power, Design Compiler, Fusion Compiler

• 22j

  Sr. Staff Physical Design Engineer

  Vancouver, BC

  Temps plein

  AI

  AMD, Inc.

  Candidates need strong experience in high-performance physical design, timing closure and physical signoff, plus proficiency in Python and TCL for flow automation. Experience leading engineers and an electronics or electrical engineering background are preferred.

  Synopsys ICC2, Fusion Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache RedHawk

  26j

  Short Term 2027 Data Analyst Intern/Co-Op

  Markham, ON

  AI

  AMD, Inc.

  Candidates need to be enrolled in a Canadian university undergraduate program in a data or engineering field. Experience with Python, SQL, R, Java, data processing, cloud services and visualization tools is strongly encouraged.

  Power BI, Snowflake, Oracle, SQL Server, Microsoft Azure, Kubernetes

  27j

  SoC Design Lead, Microarchitecture and Design Methodology

  Markham, ON

  Temps plein

  AI

  AMD, Inc.

  Candidates need a strong foundation in computer architecture and digital design, along with static timing analysis, clock and power optimization knowledge. Experience with Verilog or SystemVerilog, and UVM preferred, plus strong communication and teamwork skills.

  Verilog, SystemVerilog, UVM

  27j

  SoC Lead Engineer – LEC & Low Power Signoff

  Markham, ON

  Temps plein

  AI

  AMD, Inc.

  Candidates need proven SoC implementation and tapeout experience, in-depth LEC and low power static verification skills, and hands-on use of Formality or Conformal, VC-LP or CLP, and Design Compiler or Fusion Compiler. Verilog, VHDL, UPF, Tcl, Perl and Python skills and a BS/MS in electrical engineering or a related field are also expected.

  Synopsys Formality, Cadence Conformal, Synopsys VC-LP, Cadence Conformal Low Power, Design Compiler, Fusion Compiler

• 25j

  Production Manager, Sylvia Fedoruk Canadian Centre for Nuclear Innovation Inc.

  Saskatoon, SK

  75k–122k $/an

  

  University of Saskatchewan

  5+ ans5+ gestionCandidates need a relevant science degree (preferred), about 5 years of production or technical experience, and 5 years supervising technical staff. Knowledge of radiochemistry, radiation safety, and CNSC and Health Canada GMP rules is needed.

  Hot cells, Dose calibrators, HPLC, GC, TLC, Cyclotron

• 26j

  Staff ASIC Design Engineer – AI/ML Hardware IP

  Toronto, ON

  T

  Talentlab

  5+ ansCandidates need at least 5 years of hands-on ASIC design experience and strong skills in Verilog, SystemVerilog, and logic synthesis. A degree in electrical or computer engineering is required, and candidates must be legally authorized to work on-site in Canada.

  Verilog, SystemVerilog, Design Compiler, PrimeTime, Formality, Spyglass

• 27j

  Physical Design Engineer Intern (Toronto)

  Toronto, ON

  AL

  Astera Labs Early Career - North America 2027

  Candidates need to be pursuing a bachelor's or master's degree in electrical, computer or a related engineering field. Coursework or hands-on experience with VLSI, digital logic and timing concepts, plus Unix/Linux and a scripting language such as Tcl or Python, is needed.

  Innovus, PrimeTime, Genus, Calibre, Voltus, Tcl

  27j

  Digital Design Engineer Intern (Toronto)

  Toronto, ON

  AL

  Astera Labs Early Career - North America 2027

  Candidates need to be pursuing a bachelor's or master's degree in electrical, computer engineering, computer science or a related field. They need digital logic or RTL coursework or project experience, programming skills in Verilog, SystemVerilog, C/C++ or Python, and familiarity with Linux and Git.

  Verilog, SystemVerilog, Linux, Git, Python, Tcl

• 29j

  ASIC Physical Design Engineer - DFT, Senior

  Télétravail au Canada

  TélétravailTemps plein

  

  Positron AI

  8+ ansPositron AI needs 8+ years of ASIC development with several production tapeouts, deep DFT experience, and hands-on Siemens Tessent. Candidates also need Verilog/SystemVerilog RTL skills, synthesis and gate-level verification, and scripting in Python, Tcl or Perl.

  Siemens Tessent, Verilog, SystemVerilog, Python, Tcl, Perl

  29j

  ASIC Design Engineer, Senior

  Télétravail au Canada

  TélétravailTemps plein

  

  Positron AI

  8+ ansCandidates need a BS or MS in electrical or computer engineering with 8+ years of ASIC or SoC RTL design experience. They need deep SystemVerilog skills, front-end EDA tool expertise, and hands-on work with at least three of HBM/DDR, PCIe/CXL, AMBA AXI/ACE/CHI, cache hierarchies, or high-throughput datapaths.

  SystemVerilog, Python, Tcl, Make, UVM, cocotb

  29j

  Physical Design Engineer - Synth, Senior

  Télétravail au Canada

  TélétravailTemps plein

  

  Positron AI

  8+ ansCandidates need 8+ years of ASIC implementation experience, including at least two tapeouts, and strong synthesis and timing-closure experience on large designs. Expertise with Genus or Design Compiler, SDC constraints, Tcl and Python scripting, and advanced process nodes (7nm and below preferred) is required.

  Cadence Genus, Synopsys Design Compiler, Tcl, Python

• 1 mois

  Digital IC Designer

  Waterloo, ON

  Temps plein

  

  onsemi: With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety,…

  5+ ansCandidates need a bachelor's degree in electrical or computer engineering or equivalent, and 5 to 10+ years of direct digital IC design experience with a track record of working products. Experience with CAD tools, scripting in Python or TCL, and DSP, microcontrollers or FPGA is an asset.

  VHDL, Python, TCL, FPGA, C

• 1 mois

  ASIC Physical Design, Sr Staff Engineer - 16724

  Nepean, ON

  S

  Synopsys

  9+ ansCandidates need 9+ years of ASIC physical design experience on complex SoC or test chip projects at advanced nodes. They must know the full physical design flow and tools such as Design Compiler, PrimeTime, IC Compiler II, Calibre and RedHawk, and must be authorized to work in the USA.

  Design Compiler, PrimeTime, IC Compiler II, ICV, Calibre, RedHawk

  1 mois

  ASIC Digital Design, Architect

  Markham, ON

  S

  Synopsys

  10+ ansCandidates need a master's degree or equivalent experience and 10+ years of digital ASIC design, ideally in high-speed or mixed-signal work. They need strong Verilog or VHDL skills, clock domain crossing knowledge, synthesis and DFT experience, and experience working with verification teams.

  Verilog, VHDL, synthesis tools, DFT tools

• 1 mois

  Staff Software Engineer, Risk Engineering

  Toronto, ON

  

  Stripe: Headquartered in San Francisco and Dublin, the company aims to increase the GDP of the internet.

  10+ ansCandidates need 10+ years of software engineering experience, including 5+ years in strategic technical leadership on infrastructure or distributed systems. They must have built high-throughput, low-latency APIs at scale and communicate technical decisions clearly to non-technical stakeholders.

  Onboarding, Regulatory compliance, Anti-money laundering, ML, Debugging, Communication skills

• 1 mois

  RTL Engineer

  Burnaby, BC

  106k–158k $/anTemps plein

  SS

  SEL Schweitzer Laboratories, Inc.

  5+ ansCandidates need a B.S. in Electrical Engineering or equivalent, plus 5+ years of combined FPGA RTL design in VHDL or Verilog, firmware in C/C++, and functional verification experience. Strong technical writing, teamwork and mentoring skills are required.

  VHDL, Verilog, Xilinx tools, Intel FPGA (Altera) tools, Microchip (Microsemi/Actel) tools, Lattice Semiconductor tools

• 1 mois

  Senior ASIC Design Engineer, Compute DSP/AI Processors (multiple levels)

  Markham, ON

  Sur place

  

  Qualcomm Canada ULC

  2+ ansCandidates need a bachelor's, master's or PhD in engineering or science with 2 to 4+ years of ASIC design or verification experience, depending on degree. Strong SystemVerilog, synthesis and design tool skills and an understanding of high-performance processor design are needed.

  SystemVerilog, VCS, Synopsys Design Compiler, Cadence, Mentor, Linting tools

• 1 mois

  Senior FPGA Design Engineer

  Ottawa, ON

  Temps plein

  

  BTA Design Services: specializes in ASIC and FPGA design and verification services, custom IP development, embedded software, and DevOps capabilities creation.

  10+ ansCandidates need about 10 to 15 years of hands-on FPGA design experience and strong current SystemVerilog skills. They must handle clock domain crossings, configure synthesis tools, write SDC constraints, and analyze synthesis reports, and be available to work on-site in Ottawa.

  SystemVerilog, SDC

• 1 mois

  FPGA Design Engineer

  Burlington, ON

  70k–100k $/anTemps plein

  EM

  Evertz Microsystems Limited: Evertz Microsystems (TSX:ET) is a leading global manufacturer of broadcast equipment and solutions that deliver content to television sets,…

  1+ ansCandidates need a bachelor's degree in electrical or computer engineering, 1 to 5 years of FPGA design experience, and HDL skills in VHDL, Verilog, or SystemVerilog. Hands-on lab debugging, simulation, and familiarity with Vivado or Quartus are also required.

  Xilinx Vivado, Intel Quartus, Oscilloscopes, Waveform monitors, Git

• 1 mois

  FPGA Engineer

  Ottawa, ON

  105k–145k $/anTemps plein

  

  Q-Block Computing: Imagine instruments precise enough to probe this reality—to ask whether the cosmos operates according to Nature’s own algorithms.

  4+ ansCandidates need a related engineering degree, 4+ years of professional FPGA design and verification experience, and hands-on work with Vivado, Quartus or Lattice toolchains. They also need strong high-speed digital design skills and proficiency with oscilloscopes, logic analyzers and signal generators.

  Xilinx Vivado, Intel Quartus, Lattice toolchain, oscilloscope, logic analyzer, signal generator

14 entreprises