Senior Design/Verification Engineer
Burlington, ON +1Temps plein
S
Semtech_Canada_Corporation
5+ ansCandidates need a B.Sc. in Electrical or Computer Engineering and 5+ years of industry experience, with expert knowledge of constrained random verification (UVM, OVM, AVM or VMM) and SystemVerilog. Scripting skills in Python, TCL, Perl or C and working knowledge of Linux are also required.
SystemVerilog, UVM, Python, TCL, Perl, Linux