RTL Design Engineer
Markham, ONTemps plein
AM
Advanced Micro Devices, Inc
Candidates need a Bachelor's or Master's degree in an electrical, computer or related engineering field, strong Verilog and SystemVerilog skills, scripting experience, and knowledge of AXI, AHB and AMBA protocols. Experience with ASIC design flows and processor or security subsystems is preferred.
Verilog, SystemVerilog, Python, Tcl, Perl, Ruby
ASIC Verification Engineer, AI Networking IP
Ottawa, ONTemps plein
AM
Advanced Micro Devices, Inc
Candidates need a bachelor's or master's degree in computer or electrical engineering, plus interest in ASIC verification and digital design. Experience with SystemVerilog, C or C++, and scripting languages such as Python or Perl is an asset.
SystemVerilog, UVM, Claude Code, Codex, Python, Perl