SoC DFX Scan / ATPG Engineer
Markham, ONAMD, Inc.
Candidates need a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field, plus strong DFT fundamentals and ASIC design flow knowledge. Scripting in Python, Perl, Tcl, or Shell and Verilog/SystemVerilog familiarity are preferred.
Verilog, SystemVerilog, Python, Perl, Tcl
SoC DFX Scan / ATPG Engineer
Ottawa, ONAMD, Inc.
Candidates need a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field, plus strong DFT fundamentals and ASIC design flow knowledge. Scripting in Python, Perl, Tcl, or Shell and Verilog/SystemVerilog familiarity are preferred.
Verilog, SystemVerilog, Python, Perl, Tcl
Verification Engineer
Markham, ONAMD, Inc.
Candidates need strong SystemVerilog and UVM skills, experience with ASIC or SoC verification, and familiarity with constrained-random, coverage-driven and formal verification. A Bachelor's or Master's in computer or electrical engineering is required.
UVM, Synopsys VCS, Cadence IES, Cadence IEV, Jasper, Synopsys VC-Formal
Senior ASIC RTL Design Engineer, AI Networking IP
Ottawa, ONAMD, Inc.
Candidates need proven RTL design experience in Verilog or SystemVerilog, ASIC or FPGA delivery experience, and a bachelor's or master's degree in computer or electrical engineering. Networking or high-speed interface knowledge, such as Ethernet or PCIe, is preferred.
Verilog, SystemVerilog, Synopsys tools, Cadence tools, Siemens (Mentor) tools, Python