Emplois “ASIC simulation tools” au Canada – Page 3

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• 27j

  Software Engineer, AI & Engineering Productivity Tools

  Markham, ON

  Temps plein

  AI

  AMD, Inc.

  Candidates need production software experience, frontend skills in React, Angular or Vue, and database experience with PostgreSQL, MySQL or MongoDB. AMD also wants proficiency with AI-assisted development tools like Claude Code or Codex and familiarity with Linux environments.

  Claude Code, OpenAI Codex, Git, Linux

  27j

  Principal ASIC Design Engineer

  Markham, ON

  Temps plein

  AI

  AMD, Inc.

  Candidates need a track record of leading ASIC or silicon designs through multiple product tape-outs, plus deep RTL and microarchitecture experience. Strong communication skills and the ability to lead technical reviews are also required.

  Verilog, SystemVerilog, Python, Perl, Tcl

  27j

  Design Verification Lead

  Markham, ON

  Temps plein

  AI

  AMD, Inc.

  Candidates need a bachelor's or master's degree in electrical or computer engineering, computer science or a related field, plus UVM and SystemVerilog experience and knowledge of high-speed protocols such as PCIe, CXL or Ethernet. Scripting in Python or Perl and technical leadership skills are also needed.

  SystemVerilog, Verilog, UVM, Python, Perl

• 27j

  Digital Design Engineer Intern (Toronto)

  Toronto, ON

  AL

  Astera Labs Early Career - North America 2027

  Candidates need to be pursuing a bachelor's or master's degree in electrical, computer engineering, computer science or a related field. They need digital logic or RTL coursework or project experience, programming skills in Verilog, SystemVerilog, C/C++ or Python, and familiarity with Linux and Git.

  Verilog, SystemVerilog, Linux, Git, Python, Tcl

• 28j

  Design Verification Lead

  Markham, ON

  Temps plein

  AM

  Advanced Micro Devices, Inc

  Candidates need a Bachelor's or Master's degree in an electrical, computer or related engineering field, strong UVM and SystemVerilog skills, and experience verifying high-speed protocols such as PCIe, CXL or Ethernet. Technical leadership, mentoring and scripting in Python or Perl are preferred.

  SystemVerilog, Verilog, UVM, Python, Perl

  1 mois

  Senior ASIC RTL Design Engineer, AI Networking IP

  Ottawa, ON

  Temps plein

  AM

  Advanced Micro Devices, Inc

  Candidates need a Bachelor's or Master's in computer or electrical engineering, and strong Verilog or SystemVerilog RTL design skills. Experience delivering ASIC or FPGA products, plus networking or high-speed interface knowledge, is preferred.

  Verilog, SystemVerilog, Synopsys tools, Cadence tools, Siemens (Mentor) tools, Python

  1 mois

  RTL Design Engineer

  Markham, ON

  Temps plein

  AM

  Advanced Micro Devices, Inc

  Candidates need a Bachelor's or Master's degree in Electrical or Computer Engineering or Computer Science (Master's preferred), plus proven RTL design and verification experience. Strong Verilog, SystemVerilog, scripting, and bus protocol knowledge (AXI, AHB, AMBA) are expected.

  Verilog, Tcl, Ruby, Perl, Python, Makefile

• 29j

  ASIC Physical Design Engineer, Senior

  Télétravail au Canada

  TélétravailTemps plein

  

  Positron AI

  5+ ansCandidates need 5 to 8 years of physical design experience and at least one advanced-node tapeout. Strong Innovus or ICC2 skills and knowledge of timing, power and clock tree synthesis are required.

  Innovus, ICC2, Tempus, PrimeTime, Voltus, RedHawk

  29j

  ASIC Physical Design Engineer - Power, Senior

  Télétravail au Canada

  TélétravailTemps plein

  

  Positron AI

  8+ ansCandidates need 8+ years of ASIC design experience with a strong power focus, hands-on low-power design and UPF/CPF experience, and proficiency with PrimePower, Joules and Tcl or Python. Advanced process node experience and a track record of meeting power targets on production silicon are required.

  PrimePower, Joules, Tcl, Python, UPF, CPF

  29j

  ASIC Physical Design Engineer - DFT, Senior

  Télétravail au Canada

  TélétravailTemps plein

  

  Positron AI

  8+ ansPositron AI needs 8+ years of ASIC development with several production tapeouts, deep DFT experience, and hands-on Siemens Tessent. Candidates also need Verilog/SystemVerilog RTL skills, synthesis and gate-level verification, and scripting in Python, Tcl or Perl.

  Siemens Tessent, Verilog, SystemVerilog, Python, Tcl, Perl

  29j

  ASIC Design Engineer, Senior

  Télétravail au Canada

  TélétravailTemps plein

  

  Positron AI

  8+ ansCandidates need a BS or MS in electrical or computer engineering with 8+ years of ASIC or SoC RTL design experience. They need deep SystemVerilog skills, front-end EDA tool expertise, and hands-on work with at least three of HBM/DDR, PCIe/CXL, AMBA AXI/ACE/CHI, cache hierarchies, or high-throughput datapaths.

  SystemVerilog, Python, Tcl, Make, UVM, cocotb

  29j

  Physical Design Engineer - Synth, Senior

  Télétravail au Canada

  TélétravailTemps plein

  

  Positron AI

  8+ ansCandidates need 8+ years of ASIC implementation experience, including at least two tapeouts, and strong synthesis and timing-closure experience on large designs. Expertise with Genus or Design Compiler, SDC constraints, Tcl and Python scripting, and advanced process nodes (7nm and below preferred) is required.

  Cadence Genus, Synopsys Design Compiler, Tcl, Python

• 1 mois

  Senior Analog/mixed-signal IC Developer - Acacia - (Hybrid)

  Kanata, ON +1

  HybrideTemps plein

  

  Cisco Systems Canada Co.

  8+ ansCandidates need a BSEE or higher engineering degree with substantial experience designing, simulating and measuring high-speed ICs in at least three listed areas, such as serial links, data converters, PLLs and amplifiers.

  Cadence Virtuoso, Spectre, SpectreX, APS, Matlab, EMX

  1 mois

  Principal Analog/mixed-signal IC Developer - Acacia (Hybrid)

  Kanata, ON

  HybrideTemps plein

  

  Cisco Systems Canada Co.

  15+ ansCandidates need at least 15 years of related experience (or a master's with 10, or a PhD with 7) and hands-on design, simulation and measurement of high-speed ICs. They must have led a team on high-performance circuits.

  Cadence Virtuoso, Spectre, Calibre, EMX, Matlab

  1 mois

  Analog/mixed-signal IC Developer - Acacia (Hybrid)

  Kanata, ON +1

  HybrideTemps plein

  

  Cisco Systems Canada Co.

  8+ ansCandidates need a bachelor's with 8 years of related experience, a master's with 6, or a PhD with 3, plus hands-on experience designing, simulating and measuring high-speed ICs in at least three areas such as serial links, output drivers, PLLs, clock distribution, op-amps or equalization. Experience with FinFET/GAA technologies, high-frequency layout and Cadence tools is preferred.

  Cadence Virtuoso, Spectre, Calibre, EMX, Matlab

  1 mois

  Senior Analog/mixed-signal IC Designer - Acacia (Hybrid)

  Kanata, ON

  HybrideTemps plein

  

  Cisco Systems Canada Co.

  12+ ansCandidates need a BSEE with 12+ years, an MS with 8+ years, or a PhD with 5+ years of experience. They must have high-speed IC design experience in at least three listed areas, such as serial links, PLLs, or equalization.

  Cadence Virtuoso, Spectre, SpectreX, Calibre, EMX, Matlab

  1 mois

  Senior Mixed-Signal Designer - Acacia (Hybrid)

  Kanata, ON

  HybrideTemps plein

  

  Cisco Systems Canada Co.

  12+ ansCandidates need a bachelor's with 12 years, a master's with 8, or a PhD with 5 years of related experience, plus hands-on high-speed IC design across at least three areas such as SerDes, PLLs, clock distribution or equalization.

  Cadence Virtuoso, Spectre, Calibre, EMX, Matlab

• 1 mois

  ASIC Digital Design, Architect

  Markham, ON

  S

  Synopsys

  10+ ansCandidates need a master's degree or equivalent experience and 10+ years of digital ASIC design, ideally in high-speed or mixed-signal work. They need strong Verilog or VHDL skills, clock domain crossing knowledge, synthesis and DFT experience, and experience working with verification teams.

  Verilog, VHDL, synthesis tools, DFT tools

  1 mois

  Principal Physical Design Methodology Engineer

  Markham, ON

  S

  Synopsys

  10+ ansCandidates need a Bachelor's or Master's in Electrical or Computer Engineering and 10+ years of ASIC digital implementation experience. Deep expertise with Fusion Compiler or ICC2, high-speed IP experience, and Tcl and Python scripting are required.

  Fusion Compiler, ICC2, Innovus, PrimeTime, PrimePower, Tcl

• 1 mois

  Principal Design Verification Engineer

  Toronto, ON

  

  indie

  7+ ansCandidates need a BSEE, BSCE or BSCS and 7+ years of design verification experience. Required skills include constrained random verification with SystemVerilog and UVM, coverage-driven verification, and strong programming in C/C++ with Python, Tcl or Perl scripting.

  SystemVerilog, UVM, C, C++, Python, Tcl

• 1 mois

  Engineer - Optical Systems

  Ottawa, ON

  Sur placeContrat

  

  Huawei Technologies Canada Co., Ltd.

  Candidates need a Ph.D. or Master's in electrical engineering, optical engineering, physics or a related field, plus optoelectronic simulation experience, hands-on optical testing experience, and programming in Python, C/C++ or Julia.

  Python, C/C++, Julia

• 1 mois

  DFT Engineer, Principal

  Toronto, ON

  Sur place

  

  Qualcomm Canada ULC

  8+ ansCandidates need 10+ years of SoC experience in RTL, DFT or front-end roles, and extensive use of Siemens, Synopsys and Cadence DFT tools. Strong Verilog, VHDL and SystemVerilog skills, knowledge of JTAG, iJTAG and BIST standards, and TCL or Python scripting are expected.

  Siemens DFT tools, Cadence DFT tools, Verilog, VHDL, SystemVerilog, TCL

  1 mois

  Firmware Engineer, Principal

  Toronto, ON

  Sur place

  

  Qualcomm Canada ULC

  8+ ansCandidates need an engineering or computer science degree plus 8+ years of software engineering experience, or a master's with 7+ years. They also need 4+ years coding in C, C++, Java or Python, strong embedded firmware and lab debug skills, and team leadership experience.

  Git, Python, RISC-V

  1 mois

  DFT Engineer (Senior to Staff level)

  Toronto, ON

  Sur place

  

  Qualcomm Canada ULC

  10+ ansCandidates need a bachelor's degree in an engineering or computer science field and 10+ years of SoC design experience in RTL, DFT or front-end work. They need strong knowledge of DFT tools, Verilog, VHDL and SystemVerilog, and standards such as JTAG, iJTAG and BIST.

  Siemens DFT tools, Cadence DFT tools, Verilog, VHDL, SystemVerilog, TCL

9 entreprises