ASIC Digital Design, Architect
Markham, ONSynopsys
10+ ansCandidates need a master's degree or equivalent experience and 10+ years of digital ASIC design, ideally in high-speed or mixed-signal work. They need strong Verilog or VHDL skills, clock domain crossing knowledge, synthesis and DFT experience, and experience working with verification teams.
Verilog, VHDL, synthesis tools, DFT tools
St Staff R&D Engineer
Waterloo, ONSynopsys
5+ ansCandidates need a bachelor's or master's degree in computer science or a related field, plus 5+ years of production software experience. Strong skills in C#, .NET, Python and Angular, and the ability to design software frameworks, are required.
Angular, Python, C#, React
Principal Digital Verification Engineer
Nepean, ONSynopsys
12+ ansSynopsys candidates need 12+ years of verification experience with a BSc, 10+ years with an MSc, or 8+ years with a PhD. They need deep SystemVerilog and UVM skills, simulation and waveform debugging, C knowledge, assertion-based verification, and Linux scripting. Experience with LPDDR5/5X or LPDDR6 and emulation platforms is a plus.
SystemVerilog, UVM, waveform debugger, Linux, source control, emulation platform