Pre-Silicon Signoff Lead
Mississauga, ONSynopsys
10+ ansCandidates need an MSc or PhD in electrical or computer engineering and 10+ years of industry experience. They need deep knowledge of PCIe and Ethernet, SystemVerilog, UVM and scripting, plus proven leadership and mentoring skills.
SystemVerilog, UVM, Python, TCL, Perl, C++
ATE Test Engineer, Sr Staff Engineer - 18756
Nepean, ONSynopsys
8+ ansCandidates need 8+ years of silicon validation or ATE test experience and a degree in electrical engineering or a related field. They need strong knowledge of DDR, LPDDR and HBM protocols and JEDEC specifications, plus expertise with ATE platforms, oscilloscopes, BERTs and VB code.
Teradyne, Advantest, LTX, Credence, Introspect, oscilloscope
Validation / Verification Eng, Manager - 18754
Nepean, ONSynopsys
8+ ans3+ gestionCandidates need a Bachelor's degree in electrical engineering or a related field, 8+ years of memory interface silicon validation experience, and 3+ years managing engineering teams. Required skills include Python and C, JEDEC specifications, jitter and timing analysis, and ATE testers.
Oscilloscopes, BERT, Network analyzers, Teradyne ATE, Advantest ATE, LTX/Credence ATE
Senior Director R&D Engineering (Interface PHY / Ethernet SerDes)
Ottawa, ONSynopsys
15+ ansSynopsys needs a candidate with a BS, MS or PhD in electrical or computer engineering, 15+ years of semiconductor development, and proven leadership of engineering teams. Ethernet SerDes experience is strongly preferred.
Firmware, Team building, Customer service, Program management, Risk management, Decision making
Sr Staff Package Design Engineer
Nepean, ONSynopsys
10+ ansCandidates need 10+ years of semiconductor package design or electrical modeling experience and a bachelor's degree in electrical or electronics engineering. They must have strong skills in circuit theory, 3D EM modeling in Ansys HFSS, and clear communication in English.
Ansys HFSS, EDA tools, Windows, Linux