Senior SoC Design Engineer
Burnaby, BCMCHP Semiconductor Canada ULC
3+ ansCandidates need a Bachelor's or Master's in electrical or computer engineering and 3 to 5 years of related experience, including RTL design in SystemVerilog and Verilog. Experience with ASIC design flows, synthesis, static timing analysis and PCI-Express is valued.
Synopsys Design Compiler, Cadence Incisive, Verilog, Perl, Python, Tcl
Senior Technical Staff Engineer - Analog Design
Ottawa, ONMCHP Semiconductor Canada ULC
10+ ansCandidates need a Master's or Doctorate in Electrical Engineering or a related field and 10+ years of analog and mixed-signal IC design experience, including PLLs, DLLs, ADCs, DACs and high-speed I/O. Strong skills in Cadence tools, scripting and multi-site teamwork are required.
Cadence, Verilog-A, Skill, Python, Perl, Tcl
Ingénieur principal du personnel technique – Conception analogique/ Senior Technical Staff Engineer - Analog Design
Montréal, QCMCHP Semiconductor Canada ULC
10+ ansMaîtrise ou doctorat en génie électrique; Plus de 10 ans d’expérience en circuits intégrés analogiques et mixtes; Expérience en PLL/DLL, ADC/DAC et interfaces E/S haute vitesse
Cadence IC, Verilog-A, Skill, Python, Perl, Tcl