Clocking Systems Engineer, Staff
Toronto, ONSur place
Qualcomm Canada ULC
4+ ansQualcomm Canada ULC needs a bachelor's degree with 4+ years, a master's with 3+ years, or a PhD with 2+ years of systems engineering experience. Candidates need clocking, mixed-signal, SerDes or PLL/CDR experience, and skills in MATLAB, Python or SystemVerilog.
MATLAB, Python, SystemVerilog
Senior ASIC Design Engineer, Compute DSP/AI Processors (multiple levels)
Markham, ONSur place
Qualcomm Canada ULC
2+ ansCandidates need a bachelor's, master's or PhD in engineering or science with 2 to 4+ years of ASIC design or verification experience, depending on degree. Strong SystemVerilog, synthesis and design tool skills and an understanding of high-performance processor design are needed.
SystemVerilog, VCS, Synopsys Design Compiler, Cadence, Mentor, Linting tools