Analog Design, Sr Architect - 18729
Markham, ONSynopsys
12+ ansCandidates need at least 12 years of related experience in high-speed interfaces and mixed-signal design. They also need skills in custom analog design, simulation, verification, debugging, and writing technical specifications.
Documentation, Communication skills, Troubleshooting, Debugging
Pre-Silicon Signoff Lead
Mississauga, ONSynopsys
10+ ansCandidates need an MSc or PhD in electrical or computer engineering and 10+ years of industry experience. They need deep knowledge of PCIe and Ethernet, SystemVerilog, UVM and scripting, plus proven leadership and mentoring skills.
SystemVerilog, UVM, Python, TCL, Perl, C++
ATE Test Engineer, Sr Staff Engineer - 18756
Nepean, ONSynopsys
8+ ansCandidates need 8+ years of silicon validation or ATE test experience and a degree in electrical engineering or a related field. They need strong knowledge of DDR, LPDDR and HBM protocols and JEDEC specifications, plus expertise with ATE platforms, oscilloscopes, BERTs and VB code.
Teradyne, Advantest, LTX, Credence, Introspect, oscilloscope
Project Engineering Management, Principal Engineer
Mississauga, ONSynopsys
10+ ansCandidates need an engineering degree or equivalent experience, 10+ years of customer-facing project management, and familiarity with mixed-signal IP, SoC or ASIC development. Strong communication, MS Project, Jira, UNIX/Linux and quality management system knowledge are also required.
MS Project, Jira, UNIX, Linux