Staff Design Verification Engineer
Toronto, ONTalentlab
9+ ansCandidates need a Bachelor's or Master's in computer science, electrical engineering or a related field, plus at least 9 years of ASIC design verification experience. Strong SystemVerilog and UVM skills and advanced debugging are required.
SystemVerilog, UVM, EDA tools
Senior Design Verification Engineer
Toronto, ONTalentlab
3+ ansTalentlab needs candidates with 3 to 8 years of design verification experience and strong SystemVerilog and UVM skills. Experience with SerDes, DSP or mixed-signal designs is needed, and Ethernet and PCIe knowledge is a strong plus.
SystemVerilog, UVM, Python, Perl, C/C++, GNU Make
AI Software Engineer (C++)
Toronto, ONTalentlab
5+ ansCandidates need 5+ years of professional software engineering experience, ideally in AI/ML, embedded systems or performance optimization. They need strong C++ skills, experience with deep learning frameworks, and a bachelor's degree in a related discipline.
C++, Python, NumPy, TensorFlow, PyTorch, OpenCL