Emplois “Verilog” au Canada – Page 4

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• 15j

  Pre-Si Validation Engineer

  Toronto, ON

  Temps plein

  

  Intel Corporation

  6+ ansCandidates need a Bachelor's degree in electrical or computer engineering, 6+ years with formal verification tools and methods, SystemVerilog, and CPU architecture including cache coherence and CXL. Strong problem-solving and communication skills are expected.

  formal verification tools

  19j

  Verification Engineer – AI SoC Development

  Toronto, ON

  Temps plein

  

  Intel Corporation

  6+ ansCandidates need a bachelor's degree in electrical or computer engineering with 6+ years of experience, or a master's with 4+ years, or a PhD with 2+ years. Experience with emulators such as Palladium or Zebu, SystemVerilog, RTL design and emulation scripting is required.

  Palladium, Zebu Emulator, FPGA

• 15j

  Staff SoC Design Engineer

  Télétravail au Canada

  TélétravailTemps plein

  

  quadric

  5+ ansCandidates need a BS, MS or PhD in electrical or computer engineering, at least 5 years of SoC or ASIC front-end design, and fluency in SystemVerilog or Verilog. Strong computer architecture and low-power design skills are required.

  SystemVerilog, Verilog, VCS, NoC, PCIe, UCIe

• 16j

  Logic Design Engineer

  Kanata, ON

  72k–99k $/anTemps plein

  NC

  NXP Canada Inc.

  Candidates need a Bachelor's degree in Computer Science, Engineering or a related field, plus knowledge of Verilog RTL design, logic synthesis and timing closure. Experience with complex digital IP, networking protocols and strong teamwork and communication skills are desirable.

  Verilog, logic synthesis tools, Lint, CDC tools, LEC tools

• 18j

  RTL Design Engineer

  Markham, ON

  Temps plein

  AM

  Advanced Micro Devices, Inc

  Candidates need a Bachelor's or Master's degree in an electrical, computer or related engineering field, strong Verilog and SystemVerilog skills, scripting experience, and knowledge of AXI, AHB and AMBA protocols. Experience with ASIC design flows and processor or security subsystems is preferred.

  Verilog, SystemVerilog, Python, Tcl, Perl, Ruby

  20j

  ASIC Design Engineer, PCIe IP Enablement

  Markham, ON

  Temps plein

  AM

  Advanced Micro Devices, Inc

  Candidates need hands-on ASIC hardware design experience with end-to-end ownership of complex digital IP through tape-out. Strong RTL and Verilog skills, low-power design knowledge and a Bachelor's or Master's in electrical or computer engineering are preferred.

  Verilog HDL, UPF, CPF, Lint tools, CDC tools, Synthesis tools

  20j

  RTL Design Engineer

  Markham, ON

  Temps plein

  AM

  Advanced Micro Devices, Inc

  Candidates need a bachelor's or master's degree in electrical or computer engineering or a related field, with strong Verilog and SystemVerilog skills and knowledge of CPU and embedded processor architectures. Experience with AXI, AHB, AMBA and ASIC design tools is preferred.

  Verilog, SystemVerilog, Python, Tcl, Perl, Ruby

  25j

  GPU Design Verification Engineer

  Markham, ON

  Temps plein

  AM

  Advanced Micro Devices, Inc

  Candidates need experience with IP-level ASIC verification, UVM testbenches, Verilog and SystemVerilog, and scripting in Python or Perl. Advanced Micro Devices prefers a Bachelor's or Master's in computer or electrical engineering.

  Verilog, UVM, C/C++, Perl, Python, Makefile

• 18j

  Senior Embedded Software Designer (6+ month Contract)

  Télétravail au Canada

  TélétravailTemps plein, Contrat

  

  Kepler Communications

  6+ ansCandidates need 6+ years of embedded software experience on high-reliability systems and a bachelor's degree or equivalent practical experience. They must know C/C++, embedded Linux or RTOS, device drivers, and automated testing, and be willing to use AI-assisted engineering tools.

  Git, Yocto, OpenEmbedded, FreeRTOS, SPI, I2C

  18j

  FPGA Digital Design Engineer (6+ month Contract)

  Toronto, ON

  TélétravailTemps plein, Contrat

  

  Kepler Communications

  5+ ansCandidates need a bachelor's degree in computer or electrical engineering, 5+ years of FPGA/RTL design experience, and skill in Verilog, SystemVerilog or VHDL. They also need Xilinx Zynq or UltraScale experience, timing and clock domain crossing knowledge, and scripting skills.

  Vivado, Quartus, ModelSim, Python, Tcl

• 19j

  RTL Design Engineer

  Markham, ON

  Temps plein

  AI

  AMD, Inc.

  AMD needs candidates with a Bachelor's or Master's degree in an electrical, computer or related engineering field, with Master's preferred. Strong skills in Verilog, SystemVerilog and scripting such as Python, Tcl or Perl are expected, along with knowledge of processor subsystems and ASIC design flows.

  Verilog, SystemVerilog, Python, Tcl, Perl, Ruby

  20j

  RTL Design Engineer

  Markham, ON

  Temps plein

  AI

  AMD, Inc.

  Candidates need a strong background in RTL design, Verilog and SystemVerilog, and scripting in Python, Tcl, Perl, Ruby, or Make. Experience with AXI, AHB, AMBA protocols, ASIC design tools, and a Bachelor's or Master's degree in electrical or computer engineering are expected.

  Verilog, SystemVerilog, C-DPI, FPGA, ASIC simulation and synthesis tools

  21j

  ASIC Design Engineer, PCIe IP Enablement

  Markham, ON

  Temps plein

  AI

  AMD, Inc.

  Candidates need hands-on ASIC hardware design experience with end-to-end ownership of complex digital IP through tape-out. Strong RTL and Verilog skills, synthesis and CDC tool experience, and knowledge of low-power design are expected.

  Verilog, UPF, CPF

• 19j

  IP Design PEY Intern

  Toronto, ON

  Temps plein

  AS

  Altera Semiconductor Technology Canada ULC

  Candidates need to be currently pursuing a BS in Computer Engineering, Engineering Science, Electrical Engineering, Computer Science or a related field. They need at least 3 months of Verilog, SystemVerilog or VHDL design or verification experience and 3 months of Python, TCL, Perl, C or C++ experience.

  Quartus Prime, Verilog, SystemVerilog, VHDL

• 20j

  Spécialiste électronique

  Québec, QC

  FI

  Femtum Inc

  6+ ansBaccalauréat ou maîtrise en génie électrique ou informatique; Minimum de 6 ans d'expérience en conception électronique de produits technologiques; Expérience en conception de PCB analogiques et numériques

  logiciel de conception électronique, FPGA, microcontrôleurs, processeurs embarqués

• 20j

  Principal Analog Design Engineer-19318

  Markham, ON

  S

  Synopsys

  6+ ansCandidates need a PhD with 6+ years or a Master's with 8+ years of analog and mixed-signal IC design experience, including FinFET circuit design. Strong transistor-level CMOS and SPICE simulation skills are required.

  Spectre, HSPICE, Verilog-A, schematic entry tools, Python, Perl

  21j

  Analog Design, Architect - 18618

  Mississauga, ON

  S

  Synopsys

  10+ ansCandidates need a PhD with 10+ years or MSc with 12+ years of SerDes or high-speed analog design experience. Synopsys expects silicon-proven TX, RX and clock circuit work, transistor-level CMOS and FinFET layout skills, and some leadership of small teams.

  SPICE, Verilog-A, TCL, Perl, C, Python

• 20j

  Hardware Designer

  Télétravail au Canada

  95k–145k $/anTélétravailTemps plein

  

  Fidus Systems: Founded in 2001, Fidus Systems is a premier electronic system design and development company with specialized expertise in FPGA design, embedded…

  5+ ansCandidates need at least 5 years of electronics design experience and a degree in electrical or computer engineering. Strong knowledge of high-speed circuits, multi-layer PCB design and high-speed protocols such as PCIe, DDR4 and USB-C is required.

  OrCAD Capture CIS, Cadence Allegro, LTSpice, oscilloscope, VNA, signal generator

• 20j

  Senior ASIC Design Engineer - DSP/Analog/SerDes

  Ottawa, ON

  CC

  Celero Communications, Inc.

  10+ ansCandidates need a master's or PhD in electrical or computer engineering, 10+ years of digital ASIC design, and strong Verilog or SystemVerilog skills. Knowledge of DSP, high-speed SerDes, mixed-signal or optical communications is also required.

  Verilog, SystemVerilog, Python, Tcl, MATLAB, UVM

• 23j

  Sr FPGA Programmer - Test et Vérification DO-254

  Montréal, QC

  Temps plein

  

  Thales

  10+ ansDiplôme d'ingénieur ou Master 2 / Doctorat, 5 à 10 ans d'expérience en vérification; Maîtrise de VHDL et UVM; Expérience avec Questa ou ModelSim et outils Aldec

  Questa, ModelSim, Aldec Active-HDL, Git, DOORS, Polarion

• 23j

  Sr FPGA Programmer - Test et Vérification DO-254

  Montréal, QC

  HybrideTemps plein

  TC

  Thales Canada Inc., Avionics

  10+ ansDiplôme d'ingénieur ou Bac+5 avec 5 à 10 ans d'expérience en vérification; Maîtrise de VHDL et UVM, simulation avec Questa ou ModelSim; Connaissance approfondie de DO-254 et des métriques de code coverage

  Questa, ModelSim, Aldec Active-HDL, Git, DOORS, Polarion

  23j

  Sr FPGA Programmer - Test et Vérification DO-254

  Montréal, QC

  HybrideTemps plein

  TC

  Thales Canada Inc., Avionics

  10+ ansDiplôme d'ingénieur ou Bac+5 avec 5 à 10 ans d'expérience en vérification; Maîtrise de VHDL et UVM, simulation avec Questa ou ModelSim; Connaissance approfondie de DO-254 et des métriques de code coverage

  Questa, ModelSim, Aldec Active-HDL, Git, DOORS, Polarion

• 23j

  ASIC Verification Intern - Summer 2027

  Toronto, ON

  Temps plein

  NC

  NVIDIA Canada Dev. Inc.

  Candidates need to be pursuing a BS or MS in Electrical or Computer Engineering. They need working knowledge of computer architecture, logic design, verification, algorithms and data structures, plus strong first-principles debugging and teamwork skills.

  Verilog, SystemVerilog, UVM, FPGA, Linux, Windows

• 25j

  FPGA Design & Validation Engineer – 4G/5G Radio

  Ottawa, ON

  Contrat

  

  Myticas Consulting

  7+ ansCandidates need proven FPGA and RTL design experience, expertise in NR, LTE, eCPRI, CPRI and PTP protocols, and knowledge of the O-RAN ecosystem. Experience with UVM, Git and tools like Quartus, Vivado and MATLAB/Simulink is also required.

  Quartus, Vivado, MATLAB/Simulink, HDL Coder, Git, GitHub

15 entreprises