Senior Engineer II - Physical Design
Burnaby, BCMCHP Semiconductor Canada ULC
7+ ansCandidates need a 4-year Electrical or Electronics Engineering degree and 7.5+ years of ASIC development experience. They need hands-on skill in synthesis, static timing and place and route for high-performance designs, plus Python, Perl or TCL scripting.
Verilog, VHDL, Python, Perl, TCL
Manager- Validation Design Engineering
Burnaby, BCMCHP Semiconductor Canada ULC
12+ ansCandidates need a Bachelor's or Master's in electrical or computer engineering, 12+ years of related experience including leading engineering teams, and coaching and developing engineers. Hands-on knowledge of high-speed interfaces such as PCI Express and Ethernet, FPGA and test automation, and lab instruments is preferred.
oscilloscopes, BERT, VNA, protocol analyzers, FPGA platforms, 1.6T Ethernet testers