Firmware Design Engineer
Mount Royal, SKCadence
Solide programmation en C/C++ et Python; Compréhension des principes de communication filaire; Connaissance des circuits mixtes et du traitement numérique du signal
Firmware, Work independently, Leadership, C, C++, Python
Analog CAD Engineering specialist
Mount Royal, SK +5Cadence
Candidates need a BSEE or MSEE, prior experience in analog CAD support, and a strong understanding of circuit and layout design. Excellent communication, presentation and customer service skills are also required.
Cadence Virtuoso, Cadence Pegasus, Cadence Quantus, Cadence Composer Schematic, Virtuoso Layout
Ingénieur en conception de micrologiciel - Firmware Design Engineer
Mount Royal, SKCadence
Programmation solide en C/C++ et Python; Connaissance des communications filaires; Connaissance de la conception de circuits mixtes et du traitement numérique du signal
Firmware, Work independently, Leadership, C, C++, Python
Sr. Principal Technical Quality Engineer
Toronto, ONCadence
7+ ansCandidates need an MSEE and more than 7 years of experience in analog or digital IC design or verification, or in silicon fabrication quality. Analog IC design, defect analysis methods such as RCA, 5-Why and 8D, and strong communication and teamwork skills are valued.
ISO 9001, Quality assurance, Communication skills, Teamwork, Root cause analysis, Electronics
Ingénieur en conception de micrologiciel - Firmware Design Engineer
Mount Royal, SKCadence
Programmation solide en C/C++ et Python; Connaissance des communications filaires; Connaissance de la conception de circuits mixtes et du traitement numérique du signal
Firmware, Work independently, Leadership, C, C++, Python
Lead Digital Verification Engineer
Mount Royal, SKCadence
Candidates need an engineering degree in electrical, computer or computer science, plus understanding of verification methodologies such as UVM and metric-driven verification. Strong problem-solving skills, English communication and experience with SystemVerilog assertions are required.
SystemVerilog, UVM, Python, Perl, Ruby, Cadence tools
Principal Analog IC Designer
Toronto, ON +1Cadence
5+ ansCandidates need at least 5 years of CMOS SerDes or high-speed I/O experience, a strong grasp of jitter and signal equalization, and proficiency with circuit simulation CAD tools. An MS or PhD in EE is required.
Cadence
Principal Design Engineer
CanadaCadence
Candidates need strong mathematical and linear systems skills, deep communication systems knowledge, and strong coding for simulation and data analysis. A PhD in a mathematical or physical science is likely expected.
Detect bottlenecks, Communication skills, Data analysis, Signal processing, Sales