Physical Design Engineer
Markham, ONAdvanced Micro Devices, Inc
8+ ansCandidates need a bachelor's, master's or PhD in electrical, electronics or computer engineering, with 8, 4 or 2 years of physical design experience respectively. They need expertise in block-level place and route, timing closure, physical verification and power, performance and area optimization, plus hands-on debugging of EDA tools from Synopsys, Cadence and Siemens.
Synopsys ICC2, Cadence Innovus, Synopsys PrimeTime, Spyglass, RedHawk, Calibre
Physical Design Engineer
Markham, ONAdvanced Micro Devices, Inc
Candidates at Advanced Micro Devices need ASIC physical design experience from RTL to GDSII, strong Verilog and timing analysis skills, and hands-on tape-out experience on 3nm to 16nm SoCs. They also need experience with Synopsys, Cadence or Mentor Graphics CAD tools and a bachelor's or master's degree in electrical or computer engineering.
Synopsys tools, Cadence tools, Mentor Graphics tools, Verilog
SoC Lead Engineer – LEC & Low Power Signoff
Markham, ONAdvanced Micro Devices, Inc
Advanced Micro Devices needs candidates with proven SoC implementation and tapeout experience, deep knowledge of equivalence checking and low power verification, and hands-on use of industry EDA tools. Strong scripting, debugging, leadership and communication skills are also required, along with a BS or MS in Electrical Engineering, ECE, EEE or a related field.
Synopsys Formality, Cadence Conformal, Synopsys VC-LP, Cadence Conformal Low Power, Design Compiler, Fusion Compiler
Lead Physical Design Engineer, Place & Route
Markham, ONAdvanced Micro Devices, Inc
Candidates need deep experience with place-and-route and physical design on complex or advanced-node chips. Experience with Synopsys Fusion Compiler, Cadence and Siemens EDA tools and with TCL, Perl or Shell scripting is preferred.
Synopsys Fusion Compiler, Cadence, Siemens EDA, TCL, Perl, Shell
SoC Physical Design Implementation Lead
Markham, ONAdvanced Micro Devices, Inc
Advanced Micro Devices needs candidates with deep hands-on experience in place and route, static timing analysis and clock distribution on large SoCs. Strong skills in advanced process nodes, power optimization, CAD tools from Synopsys, Cadence and Siemens, and scripting in Tcl, Perl or Shell are expected. A Bachelor's or Master's in electrical or computer engineering is preferred.
Synopsys tools, Cadence tools, Siemens (Mentor Graphics) tools, Tcl, Perl, Shell