Physical Design Engineer
Vancouver, BCAMD, Inc.
Candidates need hands-on ASIC physical design experience from RTL to GDSII, strong Verilog and timing analysis skills, and tape-out experience on advanced nodes such as 3nm, 5nm, 7nm or 16nm. A bachelor's or master's degree in computer or electrical engineering is required.
Synopsys, Cadence, Mentor Graphics, Verilog
SoC Physical Design Implementation Lead
Markham, ONAMD, Inc.
Candidates need deep hands-on experience with place and route, static timing analysis, clock distribution and physical verification on large SoCs. Advanced process nodes, 3D stacking, and Synopsys, Cadence or Siemens CAD tools are preferred, along with Tcl, Perl or Shell scripting.
Synopsys tools, Cadence tools, Tcl, Perl, Shell
Analog/Mixed-Signal SerDes Design Engineer
Markham, ONAMD, Inc.
Candidates need a BS, MS or PhD in Electrical Engineering and experience with analog or mixed-signal circuits for SerDes links. Hands-on CMOS design at advanced nodes, proficiency with CAD tools and good communication skills are preferred.
Matlab, SPICE, CAD tools
3D IC and ADVANCED PACKAGING CAD ENGINEER
Markham, ONAMD, Inc.
Candidates need a computer or electrical engineering degree, experience in 3D-IC and advanced packaging, and hands-on work with Synopsys or Cadence EDA tools. Strong Python, TCL and Perl scripting on Linux, plus experience applying AI or LLMs to CAD or hardware design, are preferred.
Synopsys 3DIC Compiler, Synopsys EDA tools, Cadence EDA tools, Verilog, UPF, Python
Printed Circuit Board PCB Design and Layout Engineer
Markham, ONAMD, Inc.
Candidates need extensive experience designing complex printed circuit boards in tools such as Cadence Allegro, Altium or Zuken, plus a Bachelor's or Master's degree in electrical or computer engineering. Strong high-speed routing and fabrication knowledge is preferred.
Cadence Allegro, OrCAD, Altium, Zuken, PADS, ODB++
Physical Design Engineer
Markham, ONAMD, Inc.
Candidates need a bachelor's degree in an electrical, electronics or computer engineering discipline and deep experience in ASIC physical design implementation and signoff. They also need hands-on skill with industry EDA tools and power, performance and area optimization.
Synopsys ICC2, Cadence Innovus, PrimeTime, Spyglass, RedHawk, Calibre
Physical Design Engineer
Markham, ONAMD, Inc.
Candidates need hands-on ASIC physical design experience from RTL to GDSII, strong Verilog and timing analysis skills, and tape-out experience on advanced nodes such as 3nm, 5nm, 7nm or 16nm. A bachelor's or master's degree in computer or electrical engineering is required.
Synopsys, Cadence, Mentor Graphics, Verilog
STA/Constraints Engineer
Vancouver, BCAMD, Inc.
Candidates need industry experience in STA, constraints and timing signoff, and expert use of Synopsys PrimeTime and GCA (ICC2 or Fusion Compiler desired). Scripting in Perl, TCL, Shell or Python and Verilog RTL experience are valued.
ICC2, Verilog